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From: WANG Xuerui <i.qemu@xen0n.name>
To: Qi Hu <huqi@loongson.cn>, WANG Xuerui <git@xen0n.name>,
	Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] tcg/loongarch64: Implement INDEX_op_neg_i{32,64}
Date: Wed, 12 Oct 2022 17:41:39 +0800	[thread overview]
Message-ID: <6e6600c7-352f-2dc3-4513-db07f40bc6a4@xen0n.name> (raw)
In-Reply-To: <04454bbe9695bd7e5d56f4003ead653fb5719099.1665405913.git.huqi@loongson.cn>

Hi,

On 2022/10/12 17:13, Qi Hu wrote:
> Signed-off-by: Qi Hu <huqi@loongson.cn>
> ---
>   tcg/loongarch64/tcg-target.c.inc | 9 +++++++++
>   tcg/loongarch64/tcg-target.h     | 4 ++--
>   2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index a3debf6da7..f5a214a17f 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1125,6 +1125,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>           tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
>           break;
>   
> +    case INDEX_op_neg_i32:
> +        tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
> +        break;
> +    case INDEX_op_neg_i64:
> +        tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1);
> +        break;
> +
>       case INDEX_op_nor_i32:
>       case INDEX_op_nor_i64:
>           if (c2) {
> @@ -1503,6 +1510,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>       case INDEX_op_ext_i32_i64:
>       case INDEX_op_not_i32:
>       case INDEX_op_not_i64:
> +    case INDEX_op_neg_i32:
> +    case INDEX_op_neg_i64:
>       case INDEX_op_extract_i32:
>       case INDEX_op_extract_i64:
>       case INDEX_op_bswap16_i32:
> diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
> index d58a6162f2..67380b2432 100644
> --- a/tcg/loongarch64/tcg-target.h
> +++ b/tcg/loongarch64/tcg-target.h
> @@ -114,7 +114,7 @@ typedef enum {
>   #define TCG_TARGET_HAS_bswap16_i32      1
>   #define TCG_TARGET_HAS_bswap32_i32      1
>   #define TCG_TARGET_HAS_not_i32          1
> -#define TCG_TARGET_HAS_neg_i32          0
> +#define TCG_TARGET_HAS_neg_i32          1
>   #define TCG_TARGET_HAS_andc_i32         1
>   #define TCG_TARGET_HAS_orc_i32          1
>   #define TCG_TARGET_HAS_eqv_i32          0
> @@ -150,7 +150,7 @@ typedef enum {
>   #define TCG_TARGET_HAS_bswap32_i64      1
>   #define TCG_TARGET_HAS_bswap64_i64      1
>   #define TCG_TARGET_HAS_not_i64          1
> -#define TCG_TARGET_HAS_neg_i64          0
> +#define TCG_TARGET_HAS_neg_i64          1
>   #define TCG_TARGET_HAS_andc_i64         1
>   #define TCG_TARGET_HAS_orc_i64          1
>   #define TCG_TARGET_HAS_eqv_i64          0
The whole change is not necessary, if target doesn't have neg then the 
target-independent logic already makes sure a sub with the same 
semantics is emitted. This is explained in the commit message of that 
commit introducing add/sub support.


  reply	other threads:[~2022-10-12  9:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12  9:13 [PATCH 0/2] tcg/loongarch64: add neg tcg_op and direct jump support Qi Hu
2022-10-12  9:13 ` [PATCH 1/2] tcg/loongarch64: Implement INDEX_op_neg_i{32,64} Qi Hu
2022-10-12  9:41   ` WANG Xuerui [this message]
2022-10-13  1:25     ` Qi Hu
2022-10-12  9:13 ` [PATCH 2/2] tcg/loongarch64: Add direct jump support Qi Hu
2022-10-12 11:34   ` WANG Xuerui
2022-10-12 11:53     ` WANG Xuerui
2022-10-13  1:25     ` Qi Hu
2022-10-13  3:01   ` [PATCH v2] " Qi Hu
2022-10-13 18:52     ` Richard Henderson
2022-10-14  3:14       ` Qi Hu

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