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From: Auger Eric <eric.auger@redhat.com>
To: Wang Xingang <wangxingang5@huawei.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	shannon.zhaosl@gmail.com, imammedo@redhat.com, mst@redhat.com,
	marcel.apfelbaum@gmail.com, peter.maydell@linaro.org,
	ehabkost@redhat.com, richard.henderson@linaro.org,
	pbonzini@redhat.com
Cc: xieyingtai@huawei.com, cenjiahui@huawei.com
Subject: Re: [PATCH RFC RESEND v2 1/6] hw/pci/pci_host: Add iommu property for pci host
Date: Mon, 12 Apr 2021 19:36:56 +0200	[thread overview]
Message-ID: <6e6a276f-86b2-2f32-f3e0-9552f3d28a21@redhat.com> (raw)
In-Reply-To: <1616656965-23328-2-git-send-email-wangxingang5@huawei.com>

Hi Wang,

On 3/25/21 8:22 AM, Wang Xingang wrote:
> From: Xingang Wang <wangxingang5@huawei.com>
> 
> The pci host iommu property is useful to check whether
> the iommu is enabled on the pci root bus.
> 
> Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
> ---
>  hw/pci/pci.c              | 18 +++++++++++++++++-
>  hw/pci/pci_host.c         |  2 ++
>  include/hw/pci/pci.h      |  1 +
>  include/hw/pci/pci_host.h |  1 +
>  4 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index ac9a24889c..e17aa9075f 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -417,6 +417,22 @@ const char *pci_root_bus_path(PCIDevice *dev)
>      return rootbus->qbus.name;
>  }
>  
> +bool pci_root_bus_has_iommu(PCIBus *bus)
"has_iommu" is misleading as it does not mean an IOMMU is actually
instantiated but rather that if there is any, it will translate
transactions coming from this primary bus

I would rather inverse the logic and have a

"bypass_iommu" property defaulting to false

and this function dubbed something like pci_root_bus_bypass_iommu
> +{
> +    PCIBus *rootbus = bus;
> +    PCIHostState *host_bridge;
> +
> +    if (!pci_bus_is_root(bus)) {
> +        rootbus = pci_device_root_bus(bus->parent_dev);
> +    }
> +
> +    host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
> +
> +    assert(host_bridge->bus == rootbus);
> +
> +    return host_bridge->iommu;
> +}
> +
>  static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
>                                MemoryRegion *address_space_mem,
>                                MemoryRegion *address_space_io,
> @@ -2716,7 +2732,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
>  
>          iommu_bus = parent_bus;
>      }
> -    if (iommu_bus && iommu_bus->iommu_fn) {
> +    if (pci_root_bus_has_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) {
>          return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn);
>      }
>      return &address_space_memory;
> diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
> index 8ca5fadcbd..92ce213b18 100644
> --- a/hw/pci/pci_host.c
> +++ b/hw/pci/pci_host.c
> @@ -222,6 +222,8 @@ const VMStateDescription vmstate_pcihost = {
>  static Property pci_host_properties_common[] = {
>      DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
>                       mig_enabled, true),
> +    DEFINE_PROP_BOOL("pci-host-iommu-enabled", PCIHostState,
> +                     iommu, true),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index 6be4e0c460..718b5a454a 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -480,6 +480,7 @@ void pci_for_each_bus(PCIBus *bus,
>  
>  PCIBus *pci_device_root_bus(const PCIDevice *d);
>  const char *pci_root_bus_path(PCIDevice *dev);
> +bool pci_root_bus_has_iommu(PCIBus *bus);
>  PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
>  int pci_qdev_find_device(const char *id, PCIDevice **pdev);
>  void pci_bus_get_w64_range(PCIBus *bus, Range *range);
> diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h
> index 52e038c019..64128e3a19 100644
> --- a/include/hw/pci/pci_host.h
> +++ b/include/hw/pci/pci_host.h
> @@ -43,6 +43,7 @@ struct PCIHostState {
>      uint32_t config_reg;
>      bool mig_enabled;
>      PCIBus *bus;
> +    bool iommu;
>  
>      QLIST_ENTRY(PCIHostState) next;
>  };
> 
Thanks

Eric



  reply	other threads:[~2021-04-12 17:40 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-25  7:22 [PATCH RFC RESEND v2 0/6] Introduce IOMMU Option For PCI Root Bus Wang Xingang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 1/6] hw/pci/pci_host: Add iommu property for pci host Wang Xingang
2021-04-12 17:36   ` Auger Eric [this message]
2021-04-13  3:25     ` Wang Xingang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 2/6] hw/pci: Add iommu option for pci root bus Wang Xingang
2021-04-12 17:36   ` Auger Eric
2021-04-13  3:34     ` Wang Xingang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 3/6] hw/pci: Add pci_root_bus_max_bus Wang Xingang
2021-04-13  8:05   ` Auger Eric
2021-04-13 11:35     ` Xingang Wang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 4/6] hw/arm/virt-acpi-build: Add explicit idmap info in IORT table Wang Xingang
2021-04-13  9:03   ` Auger Eric
2021-04-13 12:00     ` Xingang Wang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 5/6] hw/i386/acpi-build: Add explicit scope in DMAR table Wang Xingang
2021-03-25  7:22 ` [PATCH RFC RESEND v2 6/6] hw/i386/acpi-build: Add iommu filter in IVRS table Wang Xingang
2021-03-31  9:00 ` [PATCH RFC RESEND v2 0/6] Introduce IOMMU Option For PCI Root Bus Wang Xingang

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