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([2001:b07:6468:f312:1c09:f536:3de6:228c]) by smtp.googlemail.com with ESMTPSA id md24-20020a170906ae9800b00992f8110a2bsm1344960ejb.150.2023.07.01.02.21.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Jul 2023 02:21:26 -0700 (PDT) Message-ID: <6e7f39df-1ad4-d155-6d80-37dd89a28f6a@redhat.com> Date: Sat, 1 Jul 2023 11:21:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 0/9] Collapse CPUNegativeOffsetState into CPUState Content-Language: en-US To: Anton Johansson , qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com References: <20230630122551.21766-1-anjo@rev.ng> From: Paolo Bonzini In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.095, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/30/23 14:25, Anton Johansson via wrote: > CPUNegativeOffsetState is a struct placed immediately before > CPUArchState in the ArchCPU struct. Its purpose is to ensure that > certain fields (CPUTLBDescFast, IcountDecr) lay within a small negative > offset of CPUArchState in memory. This is desired for better > code-generation on arm[32|64] and riscv hosts which has addressing > modes with 12- and 11 bits of displacement respectively. The purpose is also to ensure that general purpose registers stay close to the beginning of the CPUArchState and thus can also be accessed with a small displacement. Can you check if this becomes worse for any architecture? On some 64-bit targets, 8 bytes * 32 registers is 512 bytes and it's a substantial part of the 11 bits that are available. Paolo