qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Zhenzhong Duan" <zhenzhong.duan@intel.com>,
	"Yi Liu" <yi.l.liu@intel.com>,
	"Clément Mathieu--Drif" <clement.mathieu--drif@eviden.com>,
	"Jason Wang" <jasowang@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>
Subject: [PULL 16/48] intel_iommu: Process PASID-based iotlb invalidation
Date: Wed, 15 Jan 2025 13:09:17 -0500	[thread overview]
Message-ID: <6ebe6cf2a0663f46f94a69eca5296f608da12f2e.1736964488.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1736964487.git.mst@redhat.com>

From: Zhenzhong Duan <zhenzhong.duan@intel.com>

PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.

This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).

Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-12-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/intel_iommu_internal.h |  3 +++
 hw/i386/intel_iommu.c          | 43 ++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 22dd3faf0c..5e4e563e62 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -471,6 +471,9 @@ typedef union VTDInvDesc VTDInvDesc;
 #define VTD_INV_DESC_PIOTLB_PSI_IN_PASID  (3ULL << 4)
 #define VTD_INV_DESC_PIOTLB_DID(val)      (((val) >> 16) & VTD_DOMAIN_ID_MASK)
 #define VTD_INV_DESC_PIOTLB_PASID(val)    (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PIOTLB_AM(val)       ((val) & 0x3fULL)
+#define VTD_INV_DESC_PIOTLB_IH(val)       (((val) >> 6) & 0x1)
+#define VTD_INV_DESC_PIOTLB_ADDR(val)     ((val) & ~0xfffULL)
 #define VTD_INV_DESC_PIOTLB_RSVD_VAL0     0xfff000000000f1c0ULL
 #define VTD_INV_DESC_PIOTLB_RSVD_VAL1     0xf80ULL
 
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 95f344eb46..c45a486bf8 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -322,6 +322,28 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
     return (entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb;
 }
 
+static gboolean vtd_hash_remove_by_page_piotlb(gpointer key, gpointer value,
+                                               gpointer user_data)
+{
+    VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
+    VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
+    uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
+    uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
+
+    /*
+     * According to spec, PASID-based-IOTLB Invalidation in page granularity
+     * doesn't invalidate IOTLB entries caching second-stage (PGTT=010b)
+     * or pass-through (PGTT=100b) mappings. Nested isn't supported yet,
+     * so only need to check first-stage (PGTT=001b) mappings.
+     */
+    if (entry->pgtt != VTD_SM_PASID_ENTRY_FLT) {
+        return false;
+    }
+
+    return entry->domain_id == info->domain_id && entry->pasid == info->pasid &&
+           ((entry->gfn & info->mask) == gfn || entry->gfn == gfn_tlb);
+}
+
 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
  * IntelIOMMUState to 1.  Must be called with IOMMU lock held.
  */
@@ -2937,11 +2959,29 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
     }
 }
 
+static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
+                                       uint32_t pasid, hwaddr addr, uint8_t am)
+{
+    VTDIOTLBPageInvInfo info;
+
+    info.domain_id = domain_id;
+    info.pasid = pasid;
+    info.addr = addr;
+    info.mask = ~((1 << am) - 1);
+
+    vtd_iommu_lock(s);
+    g_hash_table_foreach_remove(s->iotlb,
+                                vtd_hash_remove_by_page_piotlb, &info);
+    vtd_iommu_unlock(s);
+}
+
 static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
                                     VTDInvDesc *inv_desc)
 {
     uint16_t domain_id;
     uint32_t pasid;
+    hwaddr addr;
+    uint8_t am;
     uint64_t mask[4] = {VTD_INV_DESC_PIOTLB_RSVD_VAL0,
                         VTD_INV_DESC_PIOTLB_RSVD_VAL1,
                         VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
@@ -2959,6 +2999,9 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
         break;
 
     case VTD_INV_DESC_PIOTLB_PSI_IN_PASID:
+        am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]);
+        addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]);
+        vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am);
         break;
 
     default:
-- 
MST



  parent reply	other threads:[~2025-01-15 18:17 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
2025-01-15 18:09 ` Michael S. Tsirkin [this message]
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
2025-01-15 22:42   ` Michael S. Tsirkin
2025-01-15 23:05     ` David Woodhouse
2025-01-16  7:05       ` Michael S. Tsirkin
2025-01-16 14:06         ` David Woodhouse
2025-01-16  7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6ebe6cf2a0663f46f94a69eca5296f608da12f2e.1736964488.git.mst@redhat.com \
    --to=mst@redhat.com \
    --cc=clement.mathieu--drif@eviden.com \
    --cc=eduardo@habkost.net \
    --cc=jasowang@redhat.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=yi.l.liu@intel.com \
    --cc=zhenzhong.duan@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).