From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsXij-0003xu-Fy for qemu-devel@nongnu.org; Sat, 31 Oct 2015 11:05:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsXif-0002XE-9W for qemu-devel@nongnu.org; Sat, 31 Oct 2015 11:05:29 -0400 Received: from mail-qg0-x236.google.com ([2607:f8b0:400d:c04::236]:35443) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsXif-0002X9-6I for qemu-devel@nongnu.org; Sat, 31 Oct 2015 11:05:25 -0400 Received: by qgbb65 with SMTP id b65so84194689qgb.2 for ; Sat, 31 Oct 2015 08:05:24 -0700 (PDT) From: Michael Davidsaver Date: Sat, 31 Oct 2015 10:05:10 -0500 Message-Id: <6ecd1084e49561b742c1e7e1963be3dc38fdb58e.1446302575.git.mdavidsaver@gmail.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH v4 2/3] armv7-m: Implement SYSRESETREQ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, crosthwaitepeter@gmail.com, Michael Davidsaver , alistair23@gmail.com Implement the SYSRESETREQ bit of the AIRCR register for armv7-m (ie. cortex-m3) to trigger a GPIO out. --- hw/intc/armv7m_nvic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3ec8408..6fc167e 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -28,6 +28,7 @@ typedef struct { MemoryRegion gic_iomem_alias; MemoryRegion container; uint32_t num_irq; + qemu_irq sysresetreq; } nvic_state; #define TYPE_NVIC "armv7m_nvic" @@ -348,10 +349,13 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { + if (value & 4) { + qemu_irq_pulse(s->sysresetreq); + } if (value & 2) { qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n"); } - if (value & 5) { + if (value & 1) { qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); } if (value & 0x700) { @@ -535,11 +539,14 @@ static void armv7m_nvic_instance_init(Object *obj) * value in the GICState struct. */ GICState *s = ARM_GIC_COMMON(obj); + DeviceState *dev = DEVICE(obj); + nvic_state *nvic = NVIC(obj); /* The ARM v7m may have anything from 0 to 496 external interrupt * IRQ lines. We default to 64. Other boards may differ and should * set the num-irq property appropriately. */ s->num_irq = 64; + qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); } static void armv7m_nvic_class_init(ObjectClass *klass, void *data) -- 2.1.4