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From: Mike Kowal <kowal@linux.ibm.com>
To: "Aditya Gupta" <adityag@linux.ibm.com>,
	"Cédric Le Goater" <clg@redhat.com>,
	"Nicholas Piggin" <npiggin@gmail.com>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
	Madhavan Srinivasan <maddy@linux.ibm.com>,
	Gautam Menghani <gautam@linux.ibm.com>,
	Miles Glenn <milesg@linux.ibm.com>,
	Ganesh Goudar <ganeshgr@linux.ibm.com>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [PATCH v10 6/8] ppc/pnv: Add ChipTOD model for Power11
Date: Mon, 6 Oct 2025 10:47:50 -0500	[thread overview]
Message-ID: <6f4c213d-37ba-4745-966c-a9aad71c09df@linux.ibm.com> (raw)
In-Reply-To: <20250925173049.891406-7-adityag@linux.ibm.com>

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On 9/25/2025 12:30 PM, Aditya Gupta wrote:
> Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
> code as the Power11 core is same as Power10 core.

Reviewed-by: Michael Kowal<kowal@linux.ibm.com>

> Reviewed-by: Cédric Le Goater<clg@redhat.com>
> Signed-off-by: Aditya Gupta<adityag@linux.ibm.com>
> ---
>   hw/ppc/pnv.c                 | 15 +++++++++
>   hw/ppc/pnv_chiptod.c         | 59 ++++++++++++++++++++++++++++++++++++
>   include/hw/ppc/pnv_chiptod.h |  2 ++
>   3 files changed, 76 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 2b4df6076c4c..f0469cdb8b65 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -2495,6 +2495,8 @@ static void pnv_chip_power11_instance_init(Object *obj)
>       object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
>       object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
>                                 "xive-fabric");
> +    object_initialize_child(obj, "chiptod", &chip11->chiptod,
> +                            TYPE_PNV11_CHIPTOD);
>       object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
>                               TYPE_PNV_N1_CHIPLET);
>   
> @@ -2653,6 +2655,19 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
>       chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
>                                               (uint64_t) PNV11_LPCM_BASE(chip));
>   
> +    /* ChipTOD */
> +    object_property_set_bool(OBJECT(&chip11->chiptod), "primary",
> +                             chip->chip_id == 0, &error_abort);
> +    object_property_set_bool(OBJECT(&chip11->chiptod), "secondary",
> +                             chip->chip_id == 1, &error_abort);
> +    object_property_set_link(OBJECT(&chip11->chiptod), "chip", OBJECT(chip),
> +                             &error_abort);
> +    if (!qdev_realize(DEVICE(&chip11->chiptod), NULL, errp)) {
> +        return;
> +    }
> +    pnv_xscom_add_subregion(chip, PNV11_XSCOM_CHIPTOD_BASE,
> +                            &chip11->chiptod.xscom_regs);
> +
>       /* HOMER (must be created before OCC) */
>       object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip),
>                                &error_abort);
> diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> index b9e9c7ba3dbb..f887a18cde8d 100644
> --- a/hw/ppc/pnv_chiptod.c
> +++ b/hw/ppc/pnv_chiptod.c
> @@ -210,6 +210,22 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD *sender,
>       }
>   }
>   
> +static void chiptod_power11_broadcast_ttype(PnvChipTOD *sender,
> +                                            uint32_t trigger)
> +{
> +    PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
> +    int i;
> +
> +    for (i = 0; i < pnv->num_chips; i++) {
> +        Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
> +        PnvChipTOD *chiptod = &chip11->chiptod;
> +
> +        if (chiptod != sender) {
> +            chiptod_receive_ttype(chiptod, trigger);
> +        }
> +    }
> +}
> +
>   static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip,
>                                                   uint32_t xscom_base)
>   {
> @@ -283,6 +299,12 @@ static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod,
>       }
>   }
>   
> +static PnvCore *chiptod_power11_tx_ttype_target(PnvChipTOD *chiptod,
> +                                               uint64_t val)
> +{
> +    return chiptod_power10_tx_ttype_target(chiptod, val);
> +}
> +
>   static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
>                                       uint64_t val, unsigned size)
>   {
> @@ -520,6 +542,42 @@ static const TypeInfo pnv_chiptod_power10_type_info = {
>       }
>   };
>   
> +static int pnv_chiptod_power11_dt_xscom(PnvXScomInterface *dev, void *fdt,
> +                             int xscom_offset)
> +{
> +    const char compat[] = "ibm,power-chiptod\0ibm,power11-chiptod";
> +
> +    return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat));
> +}
> +
> +static void pnv_chiptod_power11_class_init(ObjectClass *klass, const void *data)
> +{
> +    PnvChipTODClass *pctc = PNV_CHIPTOD_CLASS(klass);
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
> +
> +    dc->desc = "PowerNV ChipTOD Controller (Power11)";
> +    device_class_set_props(dc, pnv_chiptod_properties);
> +
> +    xdc->dt_xscom = pnv_chiptod_power11_dt_xscom;
> +
> +    pctc->broadcast_ttype = chiptod_power11_broadcast_ttype;
> +    pctc->tx_ttype_target = chiptod_power11_tx_ttype_target;
> +
> +    pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
> +}
> +
> +static const TypeInfo pnv_chiptod_power11_type_info = {
> +    .name          = TYPE_PNV11_CHIPTOD,
> +    .parent        = TYPE_PNV_CHIPTOD,
> +    .instance_size = sizeof(PnvChipTOD),
> +    .class_init    = pnv_chiptod_power11_class_init,
> +    .interfaces    = (const InterfaceInfo[]) {
> +        { TYPE_PNV_XSCOM_INTERFACE },
> +        { }
> +    }
> +};
> +
>   static void pnv_chiptod_reset(void *dev)
>   {
>       PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
> @@ -579,6 +637,7 @@ static void pnv_chiptod_register_types(void)
>       type_register_static(&pnv_chiptod_type_info);
>       type_register_static(&pnv_chiptod_power9_type_info);
>       type_register_static(&pnv_chiptod_power10_type_info);
> +    type_register_static(&pnv_chiptod_power11_type_info);
>   }
>   
>   type_init(pnv_chiptod_register_types);
> diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h
> index fde569bcbfa9..466b06560a28 100644
> --- a/include/hw/ppc/pnv_chiptod.h
> +++ b/include/hw/ppc/pnv_chiptod.h
> @@ -17,6 +17,8 @@ OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD)
>   DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD)
>   #define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10"
>   DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD)
> +#define TYPE_PNV11_CHIPTOD TYPE_PNV_CHIPTOD "-POWER11"
> +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV11_CHIPTOD, TYPE_PNV11_CHIPTOD)
>   
>   enum tod_state {
>       tod_error = 0,

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  reply	other threads:[~2025-10-06 15:48 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-25 17:30 [PATCH v10 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
2025-09-25 17:30 ` [PATCH v10 1/8] ppc/pnv: Introduce Pnv11Chip Aditya Gupta
2025-10-06 15:45   ` Mike Kowal
2025-10-06 18:24     ` Aditya Gupta
2025-10-07  5:40       ` Cédric Le Goater
2025-09-25 17:30 ` [PATCH v10 2/8] ppc/pnv: Introduce Power11 PowerNV machine Aditya Gupta
2025-10-06 15:45   ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 3/8] ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller Aditya Gupta
2025-09-25 21:02   ` Cédric Le Goater
2025-09-27 13:25     ` Aditya Gupta
2025-10-06 15:46   ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 4/8] ppc/pnv: Add XIVE2 controller to Power11 Aditya Gupta
2025-10-06 15:46   ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 5/8] ppc/pnv: Add PHB5 PCIe Host bridge " Aditya Gupta
2025-10-06 15:47   ` Mike Kowal
2025-09-25 17:30 ` [PATCH v10 6/8] ppc/pnv: Add ChipTOD model for Power11 Aditya Gupta
2025-10-06 15:47   ` Mike Kowal [this message]
2025-09-25 17:30 ` [PATCH v10 7/8] tests/powernv: Switch to buildroot images instead of op-build Aditya Gupta
2025-09-25 17:30 ` [PATCH v10 8/8] tests/powernv: Add PowerNV test for Power11 Aditya Gupta
2025-09-25 21:12 ` [PATCH v10 0/8] Power11 support for QEMU [PowerNV] Cédric Le Goater
2025-09-27 13:28   ` Aditya Gupta
2025-09-28 16:34 ` Amit Machhiwal

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