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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id h1sm10993779pfh.72.2021.05.24.06.40.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 May 2021 06:40:13 -0700 (PDT) Subject: Re: [PATCH] target/arm: Use correct SP in M-profile exception return To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210520130905.2049-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <6f9ac2a7-3a69-5a91-007a-72a38373daf9@linaro.org> Date: Mon, 24 May 2021 06:40:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210520130905.2049-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/20/21 6:09 AM, Peter Maydell wrote: > When an M-profile CPU is restoring registers from the stack on > exception return, the stack pointer to use is determined based on > bits in the magic exception return type value. We were not getting > this logic entirely correct. > > Whether we use one of the Secure stack pointers or one of the > Non-Secure stack pointers depends on the EXCRET.S bit. However, > whether we use the MSP or the PSP then depends on the SPSEL bit in > either the CONTROL_S or CONTROL_NS register. We were incorrectly > selecting MSP vs PSP based on the EXCRET.SPSEL bit. > > (In the pseudocode this is in the PopStack() function, which calls > LookUpSp_with_security_mode() which in turn looks at the relevant > CONTROL.SPSEL bit.) > > The buggy behaviour wasn't noticeable in most cases, because we write > EXCRET.SPSEL to the CONTROL.SPSEL bit for the S/NS register selected > by EXCRET.ES, so we only do the wrong thing when EXCRET.S and > EXCRET.ES are different. This will happen when secure code takes a > secure exception, which then tail-chains to a non-secure exception > which finally returns to the original secure code. > > Signed-off-by: Peter Maydell > --- > This was noticed by the Arm TF-M folks, who have a pending change > to their code which will run into the situation we mishandle. > --- Reviewed-by: Richard Henderson r~