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From: "Cédric Le Goater" <clg@kaod.org>
To: Joel Stanley <joel@jms.id.au>, Peter Maydell <peter.maydell@linaro.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 4/7] aspeed_sdmc: Init status alwlays idle
Date: Tue, 7 Aug 2018 12:27:26 +0200	[thread overview]
Message-ID: <6fd6639f-9399-ffea-9924-9ccf85efd6ec@kaod.org> (raw)
In-Reply-To: <20180807075757.7242-5-joel@jms.id.au>

On 08/07/2018 09:57 AM, Joel Stanley wrote:
> The ast2500 SDRAM training routine busy waits on the 'init cycle busy
> state' bit in DDR PHY Control/Status register #1 (MCR60).
> 
> This ensures the bit always reads zero, and allows training to
> complete with upstream u-boot on the ast2500-evb.
> 
> Signed-off-by: Joel Stanley <joel@jms.id.au>



Reviewed-by: Cédric Le Goater <clg@kaod.org>

One comment below, no need to resend for that.

> ---
>  hw/misc/aspeed_sdmc.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index 9ece545c4ffa..522e01ef8c0d 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -23,6 +23,10 @@
>  /* Configuration Register */
>  #define R_CONF            (0x04 / 4)
>  
> +/* Control/Status Register #1 (ast2500) */
> +#define R_STATUS1         (0x60 / 4)
> +#define   PHY_BUSY_STATE      BIT(0)
> +
>  /*
>   * Configuration register Ox4 (for Aspeed AST2400 SOC)
>   *
> @@ -137,6 +141,17 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
>              g_assert_not_reached();
>          }
>      }
> +    if (s->silicon_rev == AST2500_A0_SILICON_REV ||
> +            s->silicon_rev == AST2500_A1_SILICON_REV) {

Maybe use the ASPEED_IS_AST2500() ? 

It would be nice to have a set of macros we could use in the different
models testing the SoC silicon revision. How about :

#define ASPEED_AST2400 0x2
#define ASPEED_AST2500 0x4
#define ASPEED_AST2600 0x6

#define ASPEED_REVISION_MAJOR(si_rev)     (((si_rev) >> 24) & 0xff)

#define ASPEED_IS_AST2400(si_rev)  (ASPEED_REVISION_MAJOR(si_rev) == ASPEED_AST2400)
#define ASPEED_IS_AST2500(si_rev)  (ASPEED_REVISION_MAJOR(si_rev) == ASPEED_AST2500)
#define ASPEED_IS_AST2600(si_rev)  (ASPEED_REVISION_MAJOR(si_rev) == ASPEED_AST2600)


Thanks,

C.


> +        switch (addr) {
> +        case R_STATUS1:
> +            /* Will never return 'busy' */
> +            data &= ~PHY_BUSY_STATE;
> +            break;
> +        default:
> +            break;
> +        }
> +    }
>  
>      s->regs[addr] = data;
>  }
> 

  reply	other threads:[~2018-08-07 10:27 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-07  7:57 [Qemu-devel] [PATCH 0/7] arm: aspeed: Extend SDRAM controller Joel Stanley
2018-08-07  7:57 ` [Qemu-devel] [PATCH 1/7] aspeed_sdmc: Extend number of valid registers Joel Stanley
2018-08-07  9:52   ` Cédric Le Goater
2018-08-07  7:57 ` [Qemu-devel] [PATCH 2/7] aspeed_sdmc: Fix saved values Joel Stanley
2018-08-07  9:55   ` Cédric Le Goater
2018-08-07  7:57 ` [Qemu-devel] [PATCH 3/7] aspeed_sdmc: Set 'cache initial sequence' always true Joel Stanley
2018-08-07 10:13   ` Cédric Le Goater
2018-08-07  7:57 ` [Qemu-devel] [PATCH 4/7] aspeed_sdmc: Init status alwlays idle Joel Stanley
2018-08-07 10:27   ` Cédric Le Goater [this message]
2018-08-07  7:57 ` [Qemu-devel] [PATCH 5/7] aspeed_sdmc: Handle ECC training Joel Stanley
2018-08-07 10:29   ` Cédric Le Goater
2018-08-07  7:57 ` [Qemu-devel] [PATCH 6/7] aspeed: add a max_ram_size property to the memory controller Joel Stanley
2018-08-07 10:29   ` Cédric Le Goater
2018-08-07 10:33     ` [Qemu-devel] [Qemu-arm] " Cédric Le Goater
2018-08-16 12:48   ` [Qemu-devel] " Peter Maydell
2018-08-16 14:03     ` Cédric Le Goater
2018-08-07  7:57 ` [Qemu-devel] [PATCH 7/7] aspeed: Link SCU to the watchdog Joel Stanley
2018-08-07 12:23   ` Cédric Le Goater
2018-08-07 12:30 ` [Qemu-devel] [PATCH 0/7] arm: aspeed: Extend SDRAM controller Cédric Le Goater
2018-08-16 12:48   ` Peter Maydell

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