From: weiwei <liweiwei@iscas.ac.cn>
To: Mayuresh Chitale <mchitale@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, liweiwei@iscas.ac.cn
Subject: Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception
Date: Mon, 17 Oct 2022 09:37:24 +0800 [thread overview]
Message-ID: <700b21aa-df1b-6bd1-d560-e12a19f996d6@iscas.ac.cn> (raw)
In-Reply-To: <20221016124726.102129-4-mchitale@ventanamicro.com>
On 2022/10/16 20:47, Mayuresh Chitale wrote:
> This patch adds a mechanism to generate a virtual instruction
> instruction exception instead of an illegal instruction exception
> during instruction decode when virt is enabled.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
> target/riscv/translate.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index db123da5ec..8b0bd38bb2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -76,6 +76,7 @@ typedef struct DisasContext {
> to reset this known value. */
> int frm;
> RISCVMXL ol;
> + bool virt_inst_excp;
> bool virt_enabled;
> const RISCVCPUConfig *cfg_ptr;
> bool hlsx;
> @@ -243,7 +244,11 @@ static void gen_exception_illegal(DisasContext *ctx)
> {
> tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> offsetof(CPURISCVState, bins));
> - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> + if (ctx->virt_inst_excp) {
> + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> + } else {
> + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> + }
> }
>
> static void gen_exception_inst_addr_mis(DisasContext *ctx)
> @@ -1062,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
> { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
> };
>
> + ctx->virt_inst_excp = false;
> /* Check for compressed insn */
> if (insn_len(opcode) == 2) {
> if (!has_ext(ctx, RVC)) {
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
next prev parent reply other threads:[~2022-10-17 1:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-16 12:47 [PATCH v11 0/5] RISC-V Smstateen support Mayuresh Chitale
2022-10-16 12:47 ` [PATCH v11 1/5] target/riscv: Add smstateen support Mayuresh Chitale
2022-11-09 23:16 ` Alistair Francis
2022-10-16 12:47 ` [PATCH v11 2/5] target/riscv: smstateen check for h/s/envcfg Mayuresh Chitale
2022-10-16 12:47 ` [PATCH v11 3/5] target/riscv: generate virtual instruction exception Mayuresh Chitale
2022-10-17 1:37 ` weiwei [this message]
2022-11-09 23:17 ` Alistair Francis
2022-10-16 12:47 ` [PATCH v11 4/5] target/riscv: smstateen check for fcsr Mayuresh Chitale
2022-11-09 23:23 ` Alistair Francis
2022-11-20 23:35 ` Alistair Francis
2023-03-24 13:31 ` liweiwei
2023-03-28 11:07 ` Mayuresh Chitale
2022-10-16 12:47 ` [PATCH v11 5/5] target/riscv: smstateen knobs Mayuresh Chitale
2022-11-10 2:19 ` [PATCH v11 0/5] RISC-V Smstateen support Alistair Francis
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