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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-40fc88b0779sm17497647f8f.58.2025.09.29.03.34.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Sep 2025 03:34:43 -0700 (PDT) Message-ID: <70156c9c-5559-496d-8753-99f1ba5f68d1@linaro.org> Date: Mon, 29 Sep 2025 12:34:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Content-Language: en-US To: Luc Michel , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Peter Maydell , Francisco Iglesias , "Edgar E . Iglesias" , Alistair Francis , Frederic Konrad , Sai Pavan Boddu References: <20250926070806.292065-1-luc.michel@amd.com> <20250926070806.292065-39-luc.michel@amd.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250926070806.292065-39-luc.michel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/9/25 09:07, Luc Michel wrote: > Add the target field in the IRQ descriptor. This allows to target an IRQ > to another IRQ controller than the GIC(s). Other supported targets are > the PMC PPU1 CPU interrupt controller and the EAM (Error management) > device. Those two devices are currently not implemented so IRQs > targeting those will be left unconnected. This is in preparation for > versal2. > > Signed-off-by: Luc Michel > Reviewed-by: Francisco Iglesias > Reviewed-by: Edgar E. Iglesias > --- > hw/arm/xlnx-versal.c | 41 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 39 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 3d960ed2636..64744401182 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -50,18 +50,30 @@ > #include "hw/cpu/cluster.h" > #include "hw/arm/bsa.h" > > /* > * IRQ descriptor to catch the following cases: > + * - An IRQ can either connect to the GICs, to the PPU1 intc, or the the EAM > * - Multiple devices can connect to the same IRQ. They are OR'ed together. > */ > FIELD(VERSAL_IRQ, IRQ, 0, 16) > +FIELD(VERSAL_IRQ, TARGET, 16, 2) > FIELD(VERSAL_IRQ, ORED, 18, 1) > FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */ > > +typedef enum VersalIrqTarget { > + IRQ_TARGET_GIC, > + IRQ_TARGET_PPU1, > + IRQ_TARGET_EAM, Maybe declare IRQ_TARGET_RSVD here, > +} VersalIrqTarget; > + > +#define PPU1_IRQ(irq) ((IRQ_TARGET_PPU1 << R_VERSAL_IRQ_TARGET_SHIFT) | (irq)) > +#define EAM_IRQ(irq) ((IRQ_TARGET_EAM << R_VERSAL_IRQ_TARGET_SHIFT) | (irq)) > #define OR_IRQ(irq, or_idx) \ > (R_VERSAL_IRQ_ORED_MASK | ((or_idx) << R_VERSAL_IRQ_OR_IDX_SHIFT) | (irq)) > +#define PPU1_OR_IRQ(irq, or_idx) \ > + ((IRQ_TARGET_PPU1 << R_VERSAL_IRQ_TARGET_SHIFT) | OR_IRQ(irq, or_idx)) > > typedef struct VersalSimplePeriphMap { > uint64_t addr; > int irq; > } VersalSimplePeriphMap; > @@ -412,19 +424,27 @@ static qemu_irq versal_get_gic_irq(Versal *s, int irq_idx) > * Or gates are placed under the /soc/irq-or-gates QOM container. > */ > static qemu_irq versal_get_irq_or_gate_in(Versal *s, int irq_idx, > qemu_irq target_irq) > { > + static const char *TARGET_STR[] = { > + [IRQ_TARGET_GIC] = "gic", > + [IRQ_TARGET_PPU1] = "ppu1", > + [IRQ_TARGET_EAM] = "eam", > + }; > + > + VersalIrqTarget target; > Object *container = versal_get_child(s, "irq-or-gates"); > DeviceState *dev; > g_autofree char *name; > int idx, or_idx; > > idx = FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ); > or_idx = FIELD_EX32(irq_idx, VERSAL_IRQ, OR_IDX); > + target = FIELD_EX32(irq_idx, VERSAL_IRQ, TARGET); and assert(target != IRQ_TARGET_RSVD) here? > > - name = g_strdup_printf("irq[%d]", idx); > + name = g_strdup_printf("%s-irq[%d]", TARGET_STR[target], idx); > dev = DEVICE(object_resolve_path_at(container, name)); > > if (dev == NULL) { > dev = qdev_new(TYPE_OR_IRQ); > object_property_add_child(container, name, OBJECT(dev)); > @@ -436,16 +456,33 @@ static qemu_irq versal_get_irq_or_gate_in(Versal *s, int irq_idx, > return qdev_get_gpio_in(dev, or_idx); > } > > static qemu_irq versal_get_irq(Versal *s, int irq_idx) > { > + VersalIrqTarget target; > qemu_irq irq; > bool ored; > > + target = FIELD_EX32(irq_idx, VERSAL_IRQ, TARGET); > ored = FIELD_EX32(irq_idx, VERSAL_IRQ, ORED); > > - irq = versal_get_gic_irq(s, irq_idx); > + switch (target) { > + case IRQ_TARGET_EAM: > + /* EAM not implemented */ > + return NULL; > + > + case IRQ_TARGET_PPU1: > + /* PPU1 CPU not implemented */ > + return NULL; > + > + case IRQ_TARGET_GIC: > + irq = versal_get_gic_irq(s, irq_idx); > + break; > + > + default: And here 'case IRQ_TARGET_RSVD' instead. > + g_assert_not_reached(); > + } > > if (ored) { > irq = versal_get_irq_or_gate_in(s, irq_idx, irq); > } >