From: Richard Henderson <richard.henderson@linaro.org>
To: Jiajie Chen <c@jia.je>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, git@xen0n.name
Subject: Re: [PATCH 0/5] Add LoongArch v1.1 instructions
Date: Wed, 25 Oct 2023 12:04:18 -0700 [thread overview]
Message-ID: <70260625-5981-40f3-a189-afddac2a6dfa@linaro.org> (raw)
In-Reply-To: <a1784c3c-b00e-4cb6-a262-96e6cbaa5c30@jia.je>
On 10/25/23 10:13, Jiajie Chen wrote:
>> On 2023/10/24 07:26, Richard Henderson wrote:
>>> See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128 block.
>>> See target/ppc/translate.c, gen_stqcx_.
>>
>> The situation here is slightly different: aarch64 and ppc64 have both 128-bit ll and sc,
>> however LoongArch v1.1 only has 64-bit ll and 128-bit sc.
Ah, that does complicate things.
> Possibly use the combination of ll.d and ld.d:
>
>
> ll.d lo, base, 0
> ld.d hi, base, 4
>
> # do some computation
>
> sc.q lo, hi, base
>
> # try again if sc failed
>
> Then a possible implementation of gen_ll() would be: align base to 128-bit boundary, read
> 128-bit from memory, save 64-bit part to rd and record whole 128-bit data in llval. Then,
> in gen_sc_q(), it uses a 128-bit cmpxchg.
>
>
> But what about the reversed instruction pattern: ll.d hi, base, 4; ld.d lo, base 0?
It would be worth asking your hardware engineers about the bounds of legal behaviour.
Ideally there would be some very explicit language, similar to
https://developer.arm.com/documentation/ddi0487/latest/
B2.9.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
But you could do the same thing, aligning and recording the entire 128-bit quantity, then
extract the ll.d result based on address bit 6. This would complicate the implementation
of sc.d as well, but would perhaps bring us "close enough" to the actual architecture.
Note that our Arm store-exclusive implementation isn't quite in spec either. There is
quite a large comment within translate-a64.c store_exclusive() about the ways things are
not quite right. But it seems to be close enough for actual usage to succeed.
r~
next prev parent reply other threads:[~2023-10-25 19:04 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 15:29 [PATCH 0/5] Add LoongArch v1.1 instructions Jiajie Chen
2023-10-23 15:29 ` [PATCH 1/5] include/exec/memop.h: Add MO_TESB Jiajie Chen
2023-10-23 15:49 ` David Hildenbrand
2023-10-23 15:52 ` Jiajie Chen
2023-10-23 15:29 ` [PATCH 2/5] target/loongarch: Add am{swap/add}[_db].{b/h} Jiajie Chen
2023-10-23 22:50 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 3/5] target/loongarch: Add amcas[_db].{b/h/w/d} Jiajie Chen
2023-10-23 15:35 ` Jiajie Chen
2023-10-23 23:00 ` Richard Henderson
2023-10-23 22:59 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 4/5] target/loongarch: Add estimated reciprocal instructions Jiajie Chen
2023-10-23 23:02 ` Richard Henderson
2023-10-23 15:29 ` [PATCH 5/5] target/loongarch: Add llacq/screl instructions Jiajie Chen
2023-10-23 23:19 ` Richard Henderson
2023-10-23 23:26 ` [PATCH 0/5] Add LoongArch v1.1 instructions Richard Henderson
2023-10-24 6:10 ` Jiajie Chen
2023-10-25 17:13 ` Jiajie Chen
2023-10-25 19:04 ` Richard Henderson [this message]
2023-10-26 1:38 ` Jiajie Chen
2023-10-26 6:54 ` gaosong
2023-10-28 13:09 ` Jiajie Chen
2023-10-30 8:23 ` gaosong
2023-10-30 11:54 ` Jiajie Chen
2023-10-31 9:11 ` gaosong
2023-10-31 9:13 ` Jiajie Chen
2023-10-31 11:06 ` gaosong
2023-10-31 11:10 ` Jiajie Chen
2023-10-31 12:12 ` gaosong
2025-11-10 3:42 ` gaosong
2025-11-10 16:00 ` Jiajie Chen
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