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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id p9sm2248741wrg.14.2021.08.31.07.01.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Aug 2021 07:01:41 -0700 (PDT) Subject: Re: [PATCH v5 2/4] hw/arm/smmuv3: Update implementation of CFGI commands based on device SID To: chunming , peter.maydell@linaro.org References: <1629878922-173270-1-git-send-email-chunming_li1234@163.com> <1629878922-173270-3-git-send-email-chunming_li1234@163.com> From: Eric Auger Message-ID: <7089ce3e-2b15-7cf3-86d9-231c69794138@redhat.com> Date: Tue, 31 Aug 2021 16:01:39 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <1629878922-173270-3-git-send-email-chunming_li1234@163.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Received-SPF: pass client-ip=216.205.24.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.391, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.932, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Cc: renwei.liu@verisilicon.com, qemu-arm@nongnu.org, jianxian.wen@verisilicon.com, qemu-devel@nongnu.org, chunming Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Chunming On 8/25/21 10:08 AM, chunming wrote: > From: chunming > > Replace "smmuv3_flush_config" with "g_hash_table_foreach_remove". this replacement may have a potential negative impact on the performance for PCIe support, which is the main use case: a unique g_hash_table_remove() is replaced by an iteration over all the config hash keys. I wonder if you couldn't just adapt smmu_iommu_mr() and it case this latter returns NULL for the current PCIe search, look up in the platform device list: peri_sdev_list? Thanks Eric > "smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices. > > Signed-off-by: chunming > --- > hw/arm/smmuv3.c | 35 ++++++++++------------------------- > include/hw/arm/smmu-common.h | 5 ++++- > 2 files changed, 14 insertions(+), 26 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 11d7fe8423..9f3f13fb8e 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -613,14 +613,6 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev, SMMUEventInfo *event) > return cfg; > } > > -static void smmuv3_flush_config(SMMUDevice *sdev) > -{ > - SMMUv3State *s = sdev->smmu; > - SMMUState *bc = &s->smmu_state; > - > - trace_smmuv3_config_cache_inv(smmu_get_sid(sdev)); > - g_hash_table_remove(bc->configs, sdev); > -} > > static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > IOMMUAccessFlags flag, int iommu_idx) > @@ -964,22 +956,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > case SMMU_CMD_CFGI_STE: > { > uint32_t sid = CMD_SID(&cmd); > - IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid); > - SMMUDevice *sdev; > + SMMUSIDRange sid_range; > > if (CMD_SSEC(&cmd)) { > cmd_error = SMMU_CERROR_ILL; > break; > } > > - if (!mr) { > - break; > - } > - > + sid_range.start = sid; > + sid_range.end = sid; > trace_smmuv3_cmdq_cfgi_ste(sid); > - sdev = container_of(mr, SMMUDevice, iommu); > - smmuv3_flush_config(sdev); > - > + g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste, > + &sid_range); > break; > } > case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ > @@ -1006,21 +994,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > case SMMU_CMD_CFGI_CD_ALL: > { > uint32_t sid = CMD_SID(&cmd); > - IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid); > - SMMUDevice *sdev; > + SMMUSIDRange sid_range; > > if (CMD_SSEC(&cmd)) { > cmd_error = SMMU_CERROR_ILL; > break; > } > > - if (!mr) { > - break; > - } > - > + sid_range.start = sid; > + sid_range.end = sid; > trace_smmuv3_cmdq_cfgi_cd(sid); > - sdev = container_of(mr, SMMUDevice, iommu); > - smmuv3_flush_config(sdev); > + g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste, > + &sid_range); > break; > } > case SMMU_CMD_TLBI_NH_ASID: > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index 95cd12a4b5..d016455d80 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -159,7 +159,10 @@ int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, > */ > SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); > > -/* Return the iommu mr associated to @sid, or NULL if none */ > +/** > + * Return the iommu mr associated to @sid, or NULL if none > + * Only for PCI device, check smmu_find_peri_sdev for non PCI/PCIe device > + */ > IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); > > #define SMMU_IOTLB_MAX_SIZE 256