From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Date: Fri, 25 Oct 2019 16:24:37 -0700 [thread overview]
Message-ID: <70a2a77da9586b6127e7b5405bf1667a31da5fb6.1572045716.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1572045716.git.alistair.francis@wdc.com>
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 11 +++++++++++
target/riscv/cpu_helper.c | 4 ++--
target/riscv/op_helper.c | 2 +-
target/riscv/translate.c | 2 +-
4 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a2358c4956..f9389b071d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -365,8 +365,19 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#if defined(TARGET_RISCV64)
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#elif defined(TARGET_RISCV32)
+#define MSTATUS_MTL 0x00000040
+#define MSTATUS_MPV 0x00000080
+#endif
+
+#ifdef TARGET_RISCV32
+# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatush, MSTATUS_MPV)
+#else
+# define MSTATUS_MPV_ISSET(env) get_field(*env->mstatus, MSTATUS_MPV)
+#endif
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 79b2f30876..dedca3eea8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -331,7 +331,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mode = get_field(*env->mstatus, MSTATUS_MPP);
if (riscv_has_ext(env, RVH) &&
- get_field(*env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
use_background = true;
}
}
@@ -718,7 +718,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
m_mode_two_stage = env->priv == PRV_M &&
access_type != MMU_INST_FETCH &&
get_field(*env->mstatus, MSTATUS_MPRV) &&
- get_field(*env->mstatus, MSTATUS_MPV);
+ MSTATUS_MPV_ISSET(env);
hs_mode_two_stage = env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index a0a631d722..b0b9890a15 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = *env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);
+ target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
mstatus = set_field(mstatus,
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ea19ba9c5d..f0d9860429 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -754,7 +754,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
if (env->priv_ver == PRV_M &&
get_field(*env->mstatus, MSTATUS_MPRV) &&
- get_field(*env->mstatus, MSTATUS_MPV)) {
+ MSTATUS_MPV_ISSET(env)) {
ctx->virt_enabled = true;
} else if (env->priv == PRV_S &&
!riscv_cpu_virt_enabled(env) &&
--
2.23.0
next prev parent reply other threads:[~2019-10-25 23:54 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 23:23 [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-10-25 23:23 ` [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-10-25 23:23 ` [PATCH v2 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-10-25 23:23 ` [PATCH v2 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-10-25 23:23 ` [PATCH v2 07/27] target/riscv: Print priv and virt in disas log Alistair Francis
2019-10-25 23:23 ` [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-10-25 23:23 ` [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-10-25 23:23 ` [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-10-25 23:23 ` [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-10-25 23:23 ` [PATCH v2 12/27] target/riscv: Add virtual register swapping function Alistair Francis
2019-10-25 23:23 ` [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-10-25 23:23 ` [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-10-25 23:24 ` [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-10-25 23:24 ` [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-10-25 23:24 ` [PATCH v2 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-10-25 23:24 ` [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-25 23:24 ` [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-25 23:24 ` [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-25 23:24 ` [PATCH v2 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-25 23:24 ` [PATCH v2 24/27] target/riscv: Implement second stage MMU Alistair Francis
2019-10-25 23:24 ` [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-25 23:24 ` Alistair Francis [this message]
2019-10-25 23:24 ` [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
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