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From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	liwei1518@gmail.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com,
	jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v4 16/16] target/riscv: add trace-hooks for each case of sw-check exception
Date: Fri, 16 Aug 2024 15:52:34 +1000	[thread overview]
Message-ID: <70e86ba9-1764-4a2d-bee5-89a0b16ba385@linaro.org> (raw)
In-Reply-To: <20240816010711.3055425-17-debug@rivosinc.com>

On 8/16/24 11:07, Deepak Gupta wrote:
> Violations to control flow rules setup by zicfilp and zicfiss lead to
> software check exceptions. To debug and fix such sw check issues in guest
> , add trace-hooks for each case.
> 
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
>   target/riscv/helper.h                         |  3 +++
>   target/riscv/insn_trans/trans_rvi.c.inc       |  3 +++
>   target/riscv/insn_trans/trans_rvzicfiss.c.inc |  1 +
>   target/riscv/op_helper.c                      | 13 +++++++++++++
>   target/riscv/trace-events                     |  6 ++++++
>   target/riscv/translate.c                      |  2 ++
>   6 files changed, 28 insertions(+)
> 
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index e946ba61fd..6e90fbd225 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -123,6 +123,9 @@ DEF_HELPER_2(cbo_zero, void, env, tl)
>   
>   /* helper to raise sw check exception */
>   DEF_HELPER_2(raise_sw_check_excep, void, env, tl)
> +/* helper functions to trace riscv cfi violations */
> +DEF_HELPER_3(zicfilp_label_mismatch, void, env, tl, tl)
> +DEF_HELPER_3(zicfiss_ra_mismatch, void, env, tl, tl)
>   
>   /* Special functions */
>   DEF_HELPER_2(csrr, tl, env, int)
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 936b430282..7021f8d3da 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -54,6 +54,7 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a)
>               /*
>                * misaligned, according to spec we should raise sw check exception
>                */
> +            trace_zicfilp_unaligned_lpad_instr(ctx->base.pc_first);
>               gen_helper_raise_sw_check_excep(tcg_env,
>                   tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL));

Ah, no.

This performs the trace at translation time.
You want the trace at execution time.

     gen_update_pc(ctx, 0);
     gen_helper_zicfilp_unaligned_lpad(tcg_env);
     ctx->base.is_jmp = DISAS_NORETURN;


void HELPER(zicfilp_unaligned_lpad)(CPURISCVState *env)
{
     trace_zicfilp_unaligned_lpad(env->pc);
     env->sw_check_code = RISCV_EXCP_SW_CHECK_FCFI_TVAL;
     riscv_raise_exception(RISCV_EXCP_SW_CHECK, 0);
}

etc.

Nevermind the previous advice vs patch 5 saying you could inline everything; I had 
forgotten the desire for tracepoints.

You should probably add these helpers and tracepoints as you add the code.  Anything else 
is going to be a bit confusing.


r~


  reply	other threads:[~2024-08-16  5:53 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-16  1:06 [PATCH v4 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-16  2:56   ` Richard Henderson
2024-08-16  1:06 ` [PATCH v4 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-16  2:59   ` Richard Henderson
2024-08-16  6:45     ` Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-16  3:41   ` Richard Henderson
2024-08-16  6:49     ` Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-16  3:59   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 07/16] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-08-16  4:00   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-16  5:35   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 12/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-16  5:43   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 13/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-16  5:09   ` Richard Henderson
2024-08-16  6:56     ` Deepak Gupta
2024-08-16  7:28       ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 14/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 15/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 16/16] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-08-16  5:52   ` Richard Henderson [this message]
2024-08-16  7:06     ` Deepak Gupta

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