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Wed, 25 Sep 2019 08:10:33 -0700 (PDT) Subject: Re: [PATCH v2 04/20] target/mips: Clean up mips-defs.h To: Aleksandar Markovic , qemu-devel@nongnu.org References: <1569415572-19635-1-git-send-email-aleksandar.markovic@rt-rk.com> <1569415572-19635-5-git-send-email-aleksandar.markovic@rt-rk.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <7109aad7-e61e-fc0e-8fcb-2aa297f0cda5@redhat.com> Date: Wed, 25 Sep 2019 17:10:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1569415572-19635-5-git-send-email-aleksandar.markovic@rt-rk.com> Content-Language: en-US X-MC-Unique: Ai6jZfmtNTCZZaS0QKbuYA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Aleksandar, On 9/25/19 2:45 PM, Aleksandar Markovic wrote: > From: Aleksandar Markovic >=20 > Mostly fix errors and warnings reported by 'checkpatch.pl -f'. >=20 > Signed-off-by: Aleksandar Markovic > --- > target/mips/mips-defs.h | 53 ++++++++++++++++++++++++++-----------------= ------ > 1 file changed, 28 insertions(+), 25 deletions(-) >=20 > diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h > index bbf056a..938c0de 100644 > --- a/target/mips/mips-defs.h > +++ b/target/mips/mips-defs.h > @@ -2,7 +2,7 @@ > #define QEMU_MIPS_DEFS_H > =20 > /* If we want to use host float regs... */ > -//#define USE_HOST_FLOAT_REGS > +/* #define USE_HOST_FLOAT_REGS */ I'd use the same block comment for the description and the commented USE_HOST_FLOAT_REGS, like you did with MIPS_STRICT_STANDARD below. Anyway, with or without this change: Reviewed-by: Philippe Mathieu-Daud=C3=A9 > =20 > /* Real pages are variable size... */ > #define MIPS_TLB_MAX 128 > @@ -57,43 +57,46 @@ > #define ASE_MXU 0x0200000000000000ULL > =20 > /* MIPS CPU defines. */ > -#define=09=09CPU_MIPS1=09(ISA_MIPS1) > -#define=09=09CPU_MIPS2=09(CPU_MIPS1 | ISA_MIPS2) > -#define=09=09CPU_MIPS3=09(CPU_MIPS2 | ISA_MIPS3) > -#define=09=09CPU_MIPS4=09(CPU_MIPS3 | ISA_MIPS4) > -#define=09=09CPU_VR54XX=09(CPU_MIPS4 | INSN_VR54XX) > -#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) > -#define=09=09CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) > -#define=09=09CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) > +#define CPU_MIPS1 (ISA_MIPS1) > +#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) > +#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) > +#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) > +#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) > +#define CPU_R5900 (CPU_MIPS3 | INSN_R5900) > +#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) > +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) > =20 > -#define=09=09CPU_MIPS5=09(CPU_MIPS4 | ISA_MIPS5) > +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) > =20 > /* MIPS Technologies "Release 1" */ > -#define=09=09CPU_MIPS32=09(CPU_MIPS2 | ISA_MIPS32) > -#define=09=09CPU_MIPS64=09(CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) > +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) > +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) > =20 > /* MIPS Technologies "Release 2" */ > -#define=09=09CPU_MIPS32R2=09(CPU_MIPS32 | ISA_MIPS32R2) > -#define=09=09CPU_MIPS64R2=09(CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) > +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) > +#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) > =20 > /* MIPS Technologies "Release 3" */ > -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) > -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) > +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) > +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) > =20 > /* MIPS Technologies "Release 5" */ > -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) > -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) > +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) > +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) > =20 > /* MIPS Technologies "Release 6" */ > -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) > -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) > +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) > +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) > =20 > /* Wave Computing: "nanoMIPS" */ > -#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) > +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) > =20 > -/* Strictly follow the architecture standard: > - - Disallow "special" instruction handling for PMON/SPIM. > - Note that we still maintain Count/Compare to match the host clock. */ > -//#define MIPS_STRICT_STANDARD 1 > +/* > + * Strictly follow the architecture standard: > + * - Disallow "special" instruction handling for PMON/SPIM. > + * Note that we still maintain Count/Compare to match the host clock. > + * > + * #define MIPS_STRICT_STANDARD 1 > + */ > =20 > #endif /* QEMU_MIPS_DEFS_H */ >=20