* [PATCH 1/9] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 12:46 ` Anton Johansson via
2023-05-02 13:57 ` [PATCH 2/9] target/cris: " Richard Henderson
` (8 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/avr/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index a6aeae6dfa..cd82f5d591 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1492,7 +1492,7 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullwr(cpu_env, data, addr);
} else {
- tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
+ tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
}
@@ -1501,7 +1501,7 @@ static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullrd(data, cpu_env, addr);
} else {
- tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
+ tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
}
@@ -1979,7 +1979,7 @@ static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@@ -1996,7 +1996,7 @@ static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@@ -2013,7 +2013,7 @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
tcg_gen_andi_tl(L, addr, 0xff);
tcg_gen_shri_tl(addr, addr, 8);
@@ -2045,7 +2045,7 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
TCGv Rd = cpu_r[0];
TCGv addr = gen_get_zaddr();
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@@ -2058,7 +2058,7 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
TCGv Rd = cpu_r[a->rd];
TCGv addr = gen_get_zaddr();
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@@ -2071,7 +2071,7 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
TCGv Rd = cpu_r[a->rd];
TCGv addr = gen_get_zaddr();
- tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
+ tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
gen_set_zaddr(addr);
return true;
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 1/9] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 1/9] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
@ 2023-05-03 12:46 ` Anton Johansson via
0 siblings, 0 replies; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 12:46 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/avr/translate.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/9] target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-02 13:57 ` [PATCH 1/9] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 12:47 ` Anton Johansson via
2023-05-02 13:57 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
` (7 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument. In this case we can fold the calls
using the size bits of MemOp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/translate_v10.c.inc | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc
index 32338bb69b..b7b0517982 100644
--- a/target/cris/translate_v10.c.inc
+++ b/target/cris/translate_v10.c.inc
@@ -80,13 +80,9 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
/* Store only if F flag isn't set */
tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- if (size == 1) {
- tcg_gen_qemu_st8(tval, taddr, mem_index);
- } else if (size == 2) {
- tcg_gen_qemu_st16(tval, taddr, mem_index);
- } else {
- tcg_gen_qemu_st32(tval, taddr, mem_index);
- }
+
+ tcg_gen_qemu_st_tl(tval, taddr, mem_index, ctz32(size) | MO_TE);
+
gen_set_label(l1);
tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
@@ -109,13 +105,7 @@ static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
return;
}
- if (size == 1) {
- tcg_gen_qemu_st8(val, addr, mem_index);
- } else if (size == 2) {
- tcg_gen_qemu_st16(val, addr, mem_index);
- } else {
- tcg_gen_qemu_st32(val, addr, mem_index);
- }
+ tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 2/9] target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 2/9] target/cris: " Richard Henderson
@ 2023-05-03 12:47 ` Anton Johansson via
0 siblings, 0 replies; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 12:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument. In this case we can fold the calls
> using the size bits of MemOp.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/cris/translate_v10.c.inc | 18 ++++--------------
> 1 file changed, 4 insertions(+), 14 deletions(-)
>
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-02 13:57 ` [PATCH 1/9] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
2023-05-02 13:57 ` [PATCH 2/9] target/cris: " Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-02 15:27 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_* Taylor Simpson
2023-05-03 12:47 ` Anton Johansson via
2023-05-02 13:57 ` [PATCH 4/9] target/m68k: " Richard Henderson
` (6 subsequent siblings)
9 siblings, 2 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument. Importantly, this removes some incorrect
casts generated by idef-parser's gen_load().
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/macros.h | 14 ++++-----
target/hexagon/genptr.c | 8 +++---
target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
target/hexagon/translate.c | 32 ++++++++++-----------
4 files changed, 40 insertions(+), 42 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 3e162de3a7..760630de8f 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -99,37 +99,37 @@
#define MEM_LOAD1s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 1); \
- tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
} while (0)
#define MEM_LOAD1u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 1); \
- tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
} while (0)
#define MEM_LOAD2s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
- tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
} while (0)
#define MEM_LOAD2u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
- tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
} while (0)
#define MEM_LOAD4s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
- tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
} while (0)
#define MEM_LOAD4u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
- tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
} while (0)
#define MEM_LOAD8u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 8); \
- tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
+ tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
} while (0)
#define MEM_STORE1_FUNC(X) \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 502c85ae35..244063b1d2 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
{
- tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
+ tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
{
- tcg_gen_qemu_ld64(dest, vaddr, mem_index);
+ tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
@@ -678,7 +678,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
{
Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
CHECK_NOSHUF(EA, 8);
- tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
+ tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ);
}
static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
@@ -1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
}
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
- tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
+ tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
tcg_gen_addi_tl(src, src, 8);
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
}
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 86511efb62..8734218e51 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1737,36 +1737,34 @@ void gen_load_cancel(Context *c, YYLTYPE *locp)
void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
HexSignedness signedness, HexValue *ea, HexValue *dst)
{
- char size_suffix[4] = {0};
- const char *sign_suffix;
+ unsigned dst_bit_width;
+ unsigned src_bit_width;
+
/* Memop width is specified in the load macro */
assert_signedness(c, locp, signedness);
- sign_suffix = (width->imm.value > 4)
- ? ""
- : ((signedness == UNSIGNED) ? "u" : "s");
+
/* If dst is a variable, assert that is declared and load the type info */
if (dst->type == VARID) {
find_variable(c, locp, dst, dst);
}
- snprintf(size_suffix, 4, "%" PRIu64, width->imm.value * 8);
+ src_bit_width = width->imm.value * 8;
+ dst_bit_width = MAX(dst->bit_width, 32);
+
/* Lookup the effective address EA */
find_variable(c, locp, ea, ea);
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");
- OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix);
+
+ OUT(c, locp, "tcg_gen_qemu_ld_i", &dst_bit_width);
OUT(c, locp, "(");
- if (dst->bit_width > width->imm.value * 8) {
- /*
- * Cast to the correct TCG type if necessary, to avoid implict cast
- * warnings. This is needed when the width of the destination var is
- * larger than the size of the requested load.
- */
- OUT(c, locp, "(TCGv) ");
+ OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx, MO_", &src_bit_width);
+ if (signedness == SIGNED) {
+ OUT(c, locp, " | MO_SIGN");
}
- OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n");
+ OUT(c, locp, " | MO_TE);\n");
}
void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index c087f183d0..cddd7c5db4 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -627,27 +627,27 @@ void process_store(DisasContext *ctx, int slot_num)
switch (ctx->store_width[slot_num]) {
case 1:
gen_check_store_width(ctx, slot_num);
- tcg_gen_qemu_st8(hex_store_val32[slot_num],
- hex_store_addr[slot_num],
- ctx->mem_idx);
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
+ hex_store_addr[slot_num],
+ ctx->mem_idx, MO_UB);
break;
case 2:
gen_check_store_width(ctx, slot_num);
- tcg_gen_qemu_st16(hex_store_val32[slot_num],
- hex_store_addr[slot_num],
- ctx->mem_idx);
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
+ hex_store_addr[slot_num],
+ ctx->mem_idx, MO_TEUW);
break;
case 4:
gen_check_store_width(ctx, slot_num);
- tcg_gen_qemu_st32(hex_store_val32[slot_num],
- hex_store_addr[slot_num],
- ctx->mem_idx);
+ tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
+ hex_store_addr[slot_num],
+ ctx->mem_idx, MO_TEUL);
break;
case 8:
gen_check_store_width(ctx, slot_num);
- tcg_gen_qemu_st64(hex_store_val64[slot_num],
- hex_store_addr[slot_num],
- ctx->mem_idx);
+ tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
+ hex_store_addr[slot_num],
+ ctx->mem_idx, MO_TEUQ);
break;
default:
{
@@ -693,13 +693,13 @@ static void process_dczeroa(DisasContext *ctx)
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
+ tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* RE: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-02 15:27 ` Taylor Simpson
2023-05-02 15:48 ` Richard Henderson
2023-05-03 12:47 ` Anton Johansson via
1 sibling, 1 reply; 28+ messages in thread
From: Taylor Simpson @ 2023-05-02 15:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel@nongnu.org
Cc: mrolnik@gmail.com, edgar.iglesias@gmail.com, ale@rev.ng,
anjo@rev.ng, laurent@vivier.eu, philmd@linaro.org,
jiaxun.yang@flygoat.com, david@redhat.com, iii@linux.ibm.com,
thuth@redhat.com, mark.cave-ayland@ilande.co.uk,
atar4qemu@gmail.com, jcmvbkbc@gmail.com
> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, May 2, 2023 8:58 AM
> To: qemu-devel@nongnu.org
> Cc: mrolnik@gmail.com; edgar.iglesias@gmail.com; Taylor Simpson
> <tsimpson@quicinc.com>; ale@rev.ng; anjo@rev.ng; laurent@vivier.eu;
> philmd@linaro.org; jiaxun.yang@flygoat.com; david@redhat.com;
> iii@linux.ibm.com; thuth@redhat.com; mark.cave-ayland@ilande.co.uk;
> atar4qemu@gmail.com; jcmvbkbc@gmail.com
> Subject: [PATCH 3/9] target/Hexagon: Finish conversion to
> tcg_gen_qemu_{ld,st}_*
>
> Convert away from the old interface with the implicit MemOp argument.
> Importantly, this removes some incorrect casts generated by idef-parser's
> gen_load().
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/hexagon/macros.h | 14 ++++-----
> target/hexagon/genptr.c | 8 +++---
> target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
> target/hexagon/translate.c | 32 ++++++++++-----------
> 4 files changed, 40 insertions(+), 42 deletions(-)
>
> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index
> 502c85ae35..244063b1d2 100644
> --- a/target/hexagon/genptr.c
> +++ b/target/hexagon/genptr.c
> @@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv
> src)
>
> static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) @@ -
> 1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t
> dstoff, TCGv src,
> tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
> }
> for (int i = 0; i < sizeof(MMVector) / 8; i++) {
> - tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
> + tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
> tcg_gen_addi_tl(src, src, 8);
> tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
Did you intend to leave the tcg_gen_st_i64 alone or should that be converted to tcg_gen_qemu_st64.
There's a tcg_gen_st8_i64 in vec_to_qvec. Does that need to be converted?
> }
I'm curious if there's a better way to do a vector load (e.g., with tcg_gen_gvec_<something>) than a loop that does 8 bytes at a time.
Otherwise,
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 15:27 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_* Taylor Simpson
@ 2023-05-02 15:48 ` Richard Henderson
2023-05-02 19:09 ` Taylor Simpson
0 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 15:48 UTC (permalink / raw)
To: Taylor Simpson, qemu-devel@nongnu.org
On 5/2/23 16:27, Taylor Simpson wrote:
>
>
>> -----Original Message-----
>> From: Richard Henderson <richard.henderson@linaro.org>
>> Sent: Tuesday, May 2, 2023 8:58 AM
>> To: qemu-devel@nongnu.org
>> Cc: mrolnik@gmail.com; edgar.iglesias@gmail.com; Taylor Simpson
>> <tsimpson@quicinc.com>; ale@rev.ng; anjo@rev.ng; laurent@vivier.eu;
>> philmd@linaro.org; jiaxun.yang@flygoat.com; david@redhat.com;
>> iii@linux.ibm.com; thuth@redhat.com; mark.cave-ayland@ilande.co.uk;
>> atar4qemu@gmail.com; jcmvbkbc@gmail.com
>> Subject: [PATCH 3/9] target/Hexagon: Finish conversion to
>> tcg_gen_qemu_{ld,st}_*
>>
>> Convert away from the old interface with the implicit MemOp argument.
>> Importantly, this removes some incorrect casts generated by idef-parser's
>> gen_load().
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/hexagon/macros.h | 14 ++++-----
>> target/hexagon/genptr.c | 8 +++---
>> target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
>> target/hexagon/translate.c | 32 ++++++++++-----------
>> 4 files changed, 40 insertions(+), 42 deletions(-)
>>
>> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index
>> 502c85ae35..244063b1d2 100644
>> --- a/target/hexagon/genptr.c
>> +++ b/target/hexagon/genptr.c
>> @@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv
>> src)
>>
>> static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) @@ -
>> 1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t
>> dstoff, TCGv src,
>> tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
>> }
>> for (int i = 0; i < sizeof(MMVector) / 8; i++) {
>> - tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
>> + tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
>> tcg_gen_addi_tl(src, src, 8);
>> tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
>
> Did you intend to leave the tcg_gen_st_i64 alone or should that be converted to tcg_gen_qemu_st64.
>
> There's a tcg_gen_st8_i64 in vec_to_qvec. Does that need to be converted?
No, those are host stores to env, not guest stores to guest memory.
Notice the lack of "qemu" in the function names.
> I'm curious if there's a better way to do a vector load (e.g., with tcg_gen_gvec_<something>) than a loop that does 8 bytes at a time.
The best you can do at the moment is tcg_gen_qemu_ld_i128.
But there's no gvec variant to load arbitrary vector lengths.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 15:48 ` Richard Henderson
@ 2023-05-02 19:09 ` Taylor Simpson
0 siblings, 0 replies; 28+ messages in thread
From: Taylor Simpson @ 2023-05-02 19:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel@nongnu.org
> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, May 2, 2023 10:49 AM
> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org
> Subject: Re: [PATCH 3/9] target/Hexagon: Finish conversion to
> tcg_gen_qemu_{ld,st}_*
>
> On 5/2/23 16:27, Taylor Simpson wrote:
> >
> >
> >> -----Original Message-----
> >> From: Richard Henderson <richard.henderson@linaro.org>
> >> Sent: Tuesday, May 2, 2023 8:58 AM
> >> To: qemu-devel@nongnu.org
> >> Cc: mrolnik@gmail.com; edgar.iglesias@gmail.com; Taylor Simpson
> >> <tsimpson@quicinc.com>; ale@rev.ng; anjo@rev.ng; laurent@vivier.eu;
> >> philmd@linaro.org; jiaxun.yang@flygoat.com; david@redhat.com;
> >> iii@linux.ibm.com; thuth@redhat.com; mark.cave-ayland@ilande.co.uk;
> >> atar4qemu@gmail.com; jcmvbkbc@gmail.com
> >> Subject: [PATCH 3/9] target/Hexagon: Finish conversion to
> >> tcg_gen_qemu_{ld,st}_*
> >>
> >> Convert away from the old interface with the implicit MemOp argument.
> >> Importantly, this removes some incorrect casts generated by
> >> idef-parser's gen_load().
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> >> target/hexagon/macros.h | 14 ++++-----
> >> target/hexagon/genptr.c | 8 +++---
> >> target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
> >> target/hexagon/translate.c | 32 ++++++++++-----------
> >> 4 files changed, 40 insertions(+), 42 deletions(-)
> >>
> >> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index
> >> 502c85ae35..244063b1d2 100644
> >> --- a/target/hexagon/genptr.c
> >> +++ b/target/hexagon/genptr.c
> >> @@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result,
> >> TCGv
> >> src)
> >>
> >> static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
> >> @@ -
> >> 1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx,
> >> intptr_t dstoff, TCGv src,
> >> tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
> >> }
> >> for (int i = 0; i < sizeof(MMVector) / 8; i++) {
> >> - tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
> >> + tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
> >> tcg_gen_addi_tl(src, src, 8);
> >> tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
> >
> > Did you intend to leave the tcg_gen_st_i64 alone or should that be
> converted to tcg_gen_qemu_st64.
> >
> > There's a tcg_gen_st8_i64 in vec_to_qvec. Does that need to be
> converted?
>
> No, those are host stores to env, not guest stores to guest memory.
> Notice the lack of "qemu" in the function names.
>
> > I'm curious if there's a better way to do a vector load (e.g., with
> tcg_gen_gvec_<something>) than a loop that does 8 bytes at a time.
>
> The best you can do at the moment is tcg_gen_qemu_ld_i128.
> But there's no gvec variant to load arbitrary vector lengths.
OK, thanks.
Also,
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-02 15:27 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_* Taylor Simpson
@ 2023-05-03 12:47 ` Anton Johansson via
1 sibling, 0 replies; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 12:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument. Importantly, this removes some incorrect
> casts generated by idef-parser's gen_load().
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/hexagon/macros.h | 14 ++++-----
> target/hexagon/genptr.c | 8 +++---
> target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++---------
> target/hexagon/translate.c | 32 ++++++++++-----------
> 4 files changed, 40 insertions(+), 42 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 4/9] target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (2 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 13:08 ` Anton Johansson via
2023-05-02 13:57 ` [PATCH 5/9] target/mips: " Richard Henderson
` (5 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 76 ++++++++++++++---------------------------
1 file changed, 25 insertions(+), 51 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 422f4652f1..744eb3748b 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -304,23 +304,14 @@ static inline void gen_addr_fault(DisasContext *s)
static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
int sign, int index)
{
- TCGv tmp;
- tmp = tcg_temp_new_i32();
- switch(opsize) {
+ TCGv tmp = tcg_temp_new_i32();
+
+ switch (opsize) {
case OS_BYTE:
- if (sign)
- tcg_gen_qemu_ld8s(tmp, addr, index);
- else
- tcg_gen_qemu_ld8u(tmp, addr, index);
- break;
case OS_WORD:
- if (sign)
- tcg_gen_qemu_ld16s(tmp, addr, index);
- else
- tcg_gen_qemu_ld16u(tmp, addr, index);
- break;
case OS_LONG:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index,
+ opsize | (sign ? MO_SIGN : 0) | MO_TE);
break;
default:
g_assert_not_reached();
@@ -332,15 +323,11 @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
int index)
{
- switch(opsize) {
+ switch (opsize) {
case OS_BYTE:
- tcg_gen_qemu_st8(val, addr, index);
- break;
case OS_WORD:
- tcg_gen_qemu_st16(val, addr, index);
- break;
case OS_LONG:
- tcg_gen_qemu_st32(val, addr, index);
+ tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE);
break;
default:
g_assert_not_reached();
@@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
- tcg_gen_qemu_ld8s(tmp, addr, index);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
case OS_WORD:
- tcg_gen_qemu_ld16s(tmp, addr, index);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
- case OS_LONG:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_SINGLE:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_helper_extf32(cpu_env, fp, tmp);
break;
case OS_DOUBLE:
- tcg_gen_qemu_ld64(t64, addr, index);
+ tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
gen_helper_extf64(cpu_env, fp, t64);
break;
case OS_EXTENDED:
@@ -995,11 +975,11 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL);
tcg_gen_shri_i32(tmp, tmp, 16);
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_addi_i32(tmp, addr, 4);
- tcg_gen_qemu_ld64(t64, tmp, index);
+ tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ);
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
break;
case OS_PACKED:
@@ -1024,24 +1004,18 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
- gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st8(tmp, addr, index);
- break;
case OS_WORD:
- gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st16(tmp, addr, index);
- break;
case OS_LONG:
gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break;
case OS_SINGLE:
gen_helper_redf32(tmp, cpu_env, fp);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break;
case OS_DOUBLE:
gen_helper_redf64(t64, cpu_env, fp);
- tcg_gen_qemu_st64(t64, addr, index);
+ tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@@ -1050,10 +1024,10 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
}
tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_shli_i32(tmp, tmp, 16);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL);
tcg_gen_addi_i32(tmp, addr, 4);
tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
- tcg_gen_qemu_st64(t64, tmp, index);
+ tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ);
break;
case OS_PACKED:
/*
@@ -2079,14 +2053,14 @@ DISAS_INSN(movep)
if (insn & 0x80) {
for ( ; i > 0 ; i--) {
tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
- tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
+ tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
}
}
} else {
for ( ; i > 0 ; i--) {
- tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
+ tcg_gen_qemu_ld_tl(dbuf, abuf, IS_USER(s), MO_UB);
tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
@@ -4337,14 +4311,14 @@ static void m68k_copy_line(TCGv dst, TCGv src, int index)
t1 = tcg_temp_new_i64();
tcg_gen_andi_i32(addr, src, ~15);
- tcg_gen_qemu_ld64(t0, addr, index);
+ tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
- tcg_gen_qemu_ld64(t1, addr, index);
+ tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ);
tcg_gen_andi_i32(addr, dst, ~15);
- tcg_gen_qemu_st64(t0, addr, index);
+ tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
- tcg_gen_qemu_st64(t1, addr, index);
+ tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ);
}
DISAS_INSN(move16_reg)
@@ -4767,7 +4741,7 @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
tmp = tcg_temp_new();
gen_load_fcr(s, tmp, reg);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
}
static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
@@ -4776,7 +4750,7 @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
TCGv tmp;
tmp = tcg_temp_new();
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_store_fcr(s, tmp, reg);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 4/9] target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 4/9] target/m68k: " Richard Henderson
@ 2023-05-03 13:08 ` Anton Johansson via
2023-05-04 8:02 ` Richard Henderson
0 siblings, 1 reply; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 13:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/m68k/translate.c | 76 ++++++++++++++---------------------------
> 1 file changed, 25 insertions(+), 51 deletions(-)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 422f4652f1..744eb3748b 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -304,23 +304,14 @@ static inline void gen_addr_fault(DisasContext *s)
> static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
> int sign, int index)
> {
> - TCGv tmp;
> - tmp = tcg_temp_new_i32();
> - switch(opsize) {
> + TCGv tmp = tcg_temp_new_i32();
> +
> + switch (opsize) {
> case OS_BYTE:
> - if (sign)
> - tcg_gen_qemu_ld8s(tmp, addr, index);
> - else
> - tcg_gen_qemu_ld8u(tmp, addr, index);
> - break;
> case OS_WORD:
> - if (sign)
> - tcg_gen_qemu_ld16s(tmp, addr, index);
> - else
> - tcg_gen_qemu_ld16u(tmp, addr, index);
> - break;
> case OS_LONG:
> - tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_qemu_ld_tl(tmp, addr, index,
> + opsize | (sign ? MO_SIGN : 0) | MO_TE);
> break;
> default:
> g_assert_not_reached();
> @@ -332,15 +323,11 @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
> static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
> int index)
> {
> - switch(opsize) {
> + switch (opsize) {
> case OS_BYTE:
> - tcg_gen_qemu_st8(val, addr, index);
> - break;
> case OS_WORD:
> - tcg_gen_qemu_st16(val, addr, index);
> - break;
> case OS_LONG:
> - tcg_gen_qemu_st32(val, addr, index);
> + tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE);
> break;
> default:
> g_assert_not_reached();
> @@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
> tmp = tcg_temp_new();
> switch (opsize) {
> case OS_BYTE:
> - tcg_gen_qemu_ld8s(tmp, addr, index);
> - gen_helper_exts32(cpu_env, fp, tmp);
> - break;
> case OS_WORD:
> - tcg_gen_qemu_ld16s(tmp, addr, index);
> - gen_helper_exts32(cpu_env, fp, tmp);
> - break;
> - case OS_LONG:
Accidental label removal?
> - tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
> gen_helper_exts32(cpu_env, fp, tmp);
> break;
> case OS_SINGLE:
> - tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
> gen_helper_extf32(cpu_env, fp, tmp);
> break;
> case OS_DOUBLE:
> - tcg_gen_qemu_ld64(t64, addr, index);
> + tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
> gen_helper_extf64(cpu_env, fp, t64);
> break;
> case OS_EXTENDED:
> @@ -995,11 +975,11 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
> gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
> break;
> }
> - tcg_gen_qemu_ld32u(tmp, addr, index);
> + tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL);
tcg_gen_qemu_ld_tl
> tcg_gen_shri_i32(tmp, tmp, 16);
> tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
> tcg_gen_addi_i32(tmp, addr, 4);
> - tcg_gen_qemu_ld64(t64, tmp, index);
> + tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ);
> tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
> break;
> case OS_PACKED:
> @@ -1024,24 +1004,18 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
> tmp = tcg_temp_new();
> switch (opsize) {
> case OS_BYTE:
> - gen_helper_reds32(tmp, cpu_env, fp);
> - tcg_gen_qemu_st8(tmp, addr, index);
> - break;
> case OS_WORD:
> - gen_helper_reds32(tmp, cpu_env, fp);
> - tcg_gen_qemu_st16(tmp, addr, index);
> - break;
> case OS_LONG:
> gen_helper_reds32(tmp, cpu_env, fp);
> - tcg_gen_qemu_st32(tmp, addr, index);
> + tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
> break;
> case OS_SINGLE:
> gen_helper_redf32(tmp, cpu_env, fp);
> - tcg_gen_qemu_st32(tmp, addr, index);
> + tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
> break;
> case OS_DOUBLE:
> gen_helper_redf64(t64, cpu_env, fp);
> - tcg_gen_qemu_st64(t64, addr, index);
> + tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
> break;
> case OS_EXTENDED:
> if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
> @@ -1050,10 +1024,10 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
> }
> tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
> tcg_gen_shli_i32(tmp, tmp, 16);
> - tcg_gen_qemu_st32(tmp, addr, index);
> + tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL);
tcg_gen_qemu_st_tl
> tcg_gen_addi_i32(tmp, addr, 4);
> tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
> - tcg_gen_qemu_st64(t64, tmp, index);
> + tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ);
> break;
> case OS_PACKED:
> /*
> @@ -2079,14 +2053,14 @@ DISAS_INSN(movep)
> if (insn & 0x80) {
> for ( ; i > 0 ; i--) {
> tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
> - tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
> + tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB);
tcg_gen_qemu_st_tl
Otherwise:
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 4/9] target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-03 13:08 ` Anton Johansson via
@ 2023-05-04 8:02 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-04 8:02 UTC (permalink / raw)
To: anjo, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/3/23 14:08, Anton Johansson wrote:
>> @@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr,
>> TCGv_ptr fp,
>> tmp = tcg_temp_new();
>> switch (opsize) {
>> case OS_BYTE:
>> - tcg_gen_qemu_ld8s(tmp, addr, index);
>> - gen_helper_exts32(cpu_env, fp, tmp);
>> - break;
>> case OS_WORD:
>> - tcg_gen_qemu_ld16s(tmp, addr, index);
>> - gen_helper_exts32(cpu_env, fp, tmp);
>> - break;
>> - case OS_LONG:
>
> Accidental label removal?
Whoops, yes indeed.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 5/9] target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (3 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 4/9] target/m68k: " Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 13:10 ` Anton Johansson via
2023-05-02 13:57 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
` (4 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 8 ++++----
target/mips/tcg/nanomips_translate.c.inc | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 999fbb7cc1..a6ca2e5a3b 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1949,13 +1949,13 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
/* load/store instructions. */
#ifdef CONFIG_USER_ONLY
-#define OP_LD_ATOMIC(insn, fname) \
+#define OP_LD_ATOMIC(insn, memop) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
- tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
+ tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
}
@@ -1967,9 +1967,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
-OP_LD_ATOMIC(ll, ld32s);
+OP_LD_ATOMIC(ll, MO_TESL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, ld64);
+OP_LD_ATOMIC(lld, MO_TEUQ);
#endif
#undef OP_LD_ATOMIC
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 9398e28000..97b9572caa 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ);
if (cpu_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 5/9] target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 5/9] target/mips: " Richard Henderson
@ 2023-05-03 13:10 ` Anton Johansson via
0 siblings, 0 replies; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 13:10 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/tcg/translate.c | 8 ++++----
> target/mips/tcg/nanomips_translate.c.inc | 2 +-
> 2 files changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (4 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 5/9] target/mips: " Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 8:13 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld,st}_* David Hildenbrand
2023-05-04 12:28 ` Ilya Leoshkevich
2023-05-02 13:57 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
` (3 subsequent siblings)
9 siblings, 2 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 152 ++++++++++++++++-------------------
1 file changed, 71 insertions(+), 81 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 46b874e94d..a05205beb1 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1973,32 +1973,24 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
{
int l = get_field(s, l1);
TCGv_i32 vl;
+ MemOp mop;
switch (l + 1) {
case 1:
- tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
- break;
case 2:
- tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
- break;
case 4:
- tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
- break;
case 8:
- tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
- break;
+ mop = ctz32(l + 1) | MO_TE;
+ tcg_gen_qemu_ld_tl(cc_src, o->addr1, get_mem_index(s), mop);
+ tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
+ gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
+ return DISAS_NEXT;
default:
vl = tcg_constant_i32(l);
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
- gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
- return DISAS_NEXT;
}
static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
@@ -2199,7 +2191,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
TCGv_i32 t2 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t2, o->in1);
gen_helper_cvd(t1, t2);
- tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
return DISAS_NEXT;
}
@@ -2457,7 +2449,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
switch (m3) {
case 0xf:
/* Effectively a 32-bit load. */
- tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
len = 32;
goto one_insert;
@@ -2465,7 +2457,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
case 0x6:
case 0x3:
/* Effectively a 16-bit load. */
- tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
len = 16;
goto one_insert;
@@ -2474,7 +2466,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
case 0x2:
case 0x1:
/* Effectively an 8-bit load. */
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
len = 8;
goto one_insert;
@@ -2490,7 +2482,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
ccm = 0;
while (m3) {
if (m3 & 0x8) {
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
ccm |= 0xffull << pos;
@@ -2746,25 +2738,25 @@ static DisasJumpType op_llgt(DisasContext *s, DisasOps *o)
static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
return DISAS_NEXT;
}
static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
return DISAS_NEXT;
}
static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW);
return DISAS_NEXT;
}
static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW);
return DISAS_NEXT;
}
@@ -2803,7 +2795,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
static DisasJumpType op_lgat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
- tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
@@ -2825,7 +2817,8 @@ static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
- tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
+
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
@@ -2942,7 +2935,7 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
MO_TEUQ | MO_ALIGN_8);
tcg_gen_addi_i64(o->in2, o->in2, 8);
- tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ);
gen_helper_load_psw(cpu_env, t1, t2);
return DISAS_NORETURN;
}
@@ -2966,7 +2959,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* Only one register to read. */
t1 = tcg_temp_new_i64();
if (unlikely(r1 == r3)) {
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
return DISAS_NEXT;
}
@@ -2974,9 +2967,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* First load the values of the first and last registers to trigger
possible page faults. */
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
- tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
store_reg32_i64(r3, t2);
@@ -2991,7 +2984,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t2);
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
}
return DISAS_NEXT;
@@ -3006,7 +2999,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* Only one register to read. */
t1 = tcg_temp_new_i64();
if (unlikely(r1 == r3)) {
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
return DISAS_NEXT;
}
@@ -3014,9 +3007,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* First load the values of the first and last registers to trigger
possible page faults. */
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
- tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
store_reg32h_i64(r3, t2);
@@ -3031,7 +3024,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t2);
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
}
return DISAS_NEXT;
@@ -3045,7 +3038,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
/* Only one register to read. */
if (unlikely(r1 == r3)) {
- tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
return DISAS_NEXT;
}
@@ -3053,9 +3046,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
possible page faults. */
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
- tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ);
tcg_gen_mov_i64(regs[r1], t1);
/* Only two registers to read. */
@@ -3069,7 +3062,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t1);
- tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
}
return DISAS_NEXT;
}
@@ -3923,15 +3916,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
switch (s->insn->data) {
case 1: /* STOCG */
- tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ);
break;
case 0: /* STOC */
- tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL);
break;
case 2: /* STOCFH */
h = tcg_temp_new_i64();
tcg_gen_shri_i64(h, regs[r1], 32);
- tcg_gen_qemu_st32(h, a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL);
break;
default:
g_assert_not_reached();
@@ -4050,7 +4043,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0);
/* load the third operand into r3 before modifying anything */
- tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ);
/* subtract CPU timer from first operand and store in GR0 */
gen_helper_stpt(tmp, cpu_env);
@@ -4128,9 +4121,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
tcg_gen_shri_i64(c1, c1, 8);
tcg_gen_ori_i64(c2, c2, 0x10000);
tcg_gen_or_i64(c2, c2, todpr);
- tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ);
tcg_gen_addi_i64(o->in2, o->in2, 8);
- tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@@ -4343,7 +4336,7 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
restart, we'll have the wrong SYSTEM MASK in place. */
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, psw_mask, 56);
- tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
if (s->fields.op == 0xac) {
tcg_gen_andi_i64(psw_mask, psw_mask,
@@ -4380,13 +4373,13 @@ static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
static DisasJumpType op_st8(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
return DISAS_NEXT;
}
static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW);
return DISAS_NEXT;
}
@@ -4424,7 +4417,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0xf:
/* Effectively a 32-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
break;
case 0xc:
@@ -4432,7 +4425,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0x3:
/* Effectively a 16-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
break;
case 0x8:
@@ -4441,7 +4434,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0x1:
/* Effectively an 8-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
break;
default:
@@ -4450,7 +4443,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
while (m3) {
if (m3 & 0x8) {
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
}
m3 = (m3 << 1) & 0xf;
@@ -4469,11 +4462,8 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
TCGv_i64 tsize = tcg_constant_i64(size);
while (1) {
- if (size == 8) {
- tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
- } else {
- tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
- }
+ tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s),
+ size == 8 ? MO_TEUQ : MO_TEUL);
if (r1 == r3) {
break;
}
@@ -4494,7 +4484,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
while (1) {
tcg_gen_shl_i64(t, regs[r1], t32);
- tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL);
if (r1 == r3) {
break;
}
@@ -4804,28 +4794,28 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
l++;
while (l >= 8) {
- tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ);
l -= 8;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 8);
}
}
if (l >= 4) {
- tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL);
l -= 4;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 4);
}
}
if (l >= 2) {
- tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW);
l -= 2;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 2);
}
}
if (l) {
- tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
}
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@@ -5314,13 +5304,13 @@ static void wout_cond_e1e2(DisasContext *s, DisasOps *o)
static void wout_m1_8(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_wout_m1_8 0
static void wout_m1_16(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW);
}
#define SPEC_wout_m1_16 0
@@ -5334,7 +5324,7 @@ static void wout_m1_16a(DisasContext *s, DisasOps *o)
static void wout_m1_32(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL);
}
#define SPEC_wout_m1_32 0
@@ -5348,7 +5338,7 @@ static void wout_m1_32a(DisasContext *s, DisasOps *o)
static void wout_m1_64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ);
}
#define SPEC_wout_m1_64 0
@@ -5362,7 +5352,7 @@ static void wout_m1_64a(DisasContext *s, DisasOps *o)
static void wout_m2_32(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
}
#define SPEC_wout_m2_32 0
@@ -5557,7 +5547,7 @@ static void in1_m1_8u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_in1_m1_8u 0
@@ -5565,7 +5555,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW);
}
#define SPEC_in1_m1_16s 0
@@ -5573,7 +5563,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW);
}
#define SPEC_in1_m1_16u 0
@@ -5581,7 +5571,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL);
}
#define SPEC_in1_m1_32s 0
@@ -5589,7 +5579,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL);
}
#define SPEC_in1_m1_32u 0
@@ -5597,7 +5587,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ);
}
#define SPEC_in1_m1_64 0
@@ -5811,35 +5801,35 @@ static void in2_sh(DisasContext *s, DisasOps *o)
static void in2_m2_8u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
}
#define SPEC_in2_m2_8u 0
static void in2_m2_16s(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW);
}
#define SPEC_in2_m2_16s 0
static void in2_m2_16u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW);
}
#define SPEC_in2_m2_16u 0
static void in2_m2_32s(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL);
}
#define SPEC_in2_m2_32s 0
static void in2_m2_32u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL);
}
#define SPEC_in2_m2_32u 0
@@ -5855,14 +5845,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *o)
static void in2_m2_64(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
}
#define SPEC_in2_m2_64 0
static void in2_m2_64w(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
}
#define SPEC_in2_m2_64w 0
@@ -5879,14 +5869,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o)
static void in2_mri2_16s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16s(o->in2, gen_ri2(s), get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW);
}
#define SPEC_in2_mri2_16s 0
static void in2_mri2_16u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16u(o->in2, gen_ri2(s), get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW);
}
#define SPEC_in2_mri2_16u 0
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-03 8:13 ` David Hildenbrand
2023-05-04 12:28 ` Ilya Leoshkevich
1 sibling, 0 replies; 28+ messages in thread
From: David Hildenbrand @ 2023-05-03 8:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, iii, thuth, mark.cave-ayland, atar4qemu, jcmvbkbc
On 02.05.23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-03 8:13 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld,st}_* David Hildenbrand
@ 2023-05-04 12:28 ` Ilya Leoshkevich
1 sibling, 0 replies; 28+ messages in thread
From: Ilya Leoshkevich @ 2023-05-04 12:28 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, thuth, mark.cave-ayland, atar4qemu, jcmvbkbc
On Tue, 2023-05-02 at 14:57 +0100, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 152 ++++++++++++++++-----------------
> --
> 1 file changed, 71 insertions(+), 81 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (5 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 6/9] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-03 13:19 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld,st}_* Anton Johansson via
2023-05-03 20:11 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Mark Cave-Ayland
2023-05-02 13:57 ` [PATCH 8/9] target/xtensa: " Richard Henderson
` (2 subsequent siblings)
9 siblings, 2 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 43 ++++++++++++++++++++++++++--------------
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 137bdc5159..bc71e44e66 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5179,15 +5179,18 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (xop) {
case 0x0: /* ld, V9 lduw, load unsigned word */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUL);
break;
case 0x1: /* ldub, load unsigned byte */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_UB);
break;
case 0x2: /* lduh, load unsigned halfword */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUW);
break;
case 0x3: /* ldd, load double word */
if (rd & 1)
@@ -5197,7 +5200,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_address_mask(dc, cpu_addr);
t64 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_i64(t64, cpu_addr,
+ dc->mem_idx, MO_TEUQ);
tcg_gen_trunc_i64_tl(cpu_val, t64);
tcg_gen_ext32u_tl(cpu_val, cpu_val);
gen_store_gpr(dc, rd + 1, cpu_val);
@@ -5208,11 +5212,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x9: /* ldsb, load signed byte */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
break;
case 0xa: /* ldsh, load signed halfword */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TESW);
break;
case 0xd: /* ldstub */
gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
@@ -5266,11 +5271,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
case 0x08: /* V9 ldsw */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TESL);
break;
case 0x0b: /* V9 ldx */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUQ);
break;
case 0x18: /* V9 ldswa */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
@@ -5369,15 +5376,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (xop) {
case 0x4: /* st, store word */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUL);
break;
case 0x5: /* stb, store byte */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
break;
case 0x6: /* sth, store halfword */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUW);
break;
case 0x7: /* std, store double word */
if (rd & 1)
@@ -5390,7 +5399,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
lo = gen_load_gpr(dc, rd + 1);
t64 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t64, lo, cpu_val);
- tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_i64(t64, cpu_addr,
+ dc->mem_idx, MO_TEUQ);
}
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -5413,7 +5423,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
case 0x0e: /* V9 stx */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
+ dc->mem_idx, MO_TEUQ);
break;
case 0x1e: /* V9 stxa */
gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
@@ -5438,11 +5449,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
if (rd == 1) {
- tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
+ dc->mem_idx, MO_TEUQ);
break;
}
#endif
- tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
+ dc->mem_idx, MO_TEUL);
}
break;
case 0x26:
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld,st}_*
2023-05-02 13:57 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-03 13:19 ` Anton Johansson via
2023-05-03 20:11 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Mark Cave-Ayland
1 sibling, 0 replies; 28+ messages in thread
From: Anton Johansson via @ 2023-05-03 13:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
On 5/2/23 15:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/sparc/translate.c | 43 ++++++++++++++++++++++++++--------------
> 1 file changed, 28 insertions(+), 15 deletions(-)
>
Reviewed-by: Anton Johansson <anjo@rev.ng>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-03 13:19 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld,st}_* Anton Johansson via
@ 2023-05-03 20:11 ` Mark Cave-Ayland
2023-05-04 7:59 ` Richard Henderson
1 sibling, 1 reply; 28+ messages in thread
From: Mark Cave-Ayland @ 2023-05-03 20:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, atar4qemu, jcmvbkbc
On 02/05/2023 14:57, Richard Henderson wrote:
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/sparc/translate.c | 43 ++++++++++++++++++++++++++--------------
> 1 file changed, 28 insertions(+), 15 deletions(-)
>
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index 137bdc5159..bc71e44e66 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -5179,15 +5179,18 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> switch (xop) {
> case 0x0: /* ld, V9 lduw, load unsigned word */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUL);
> break;
> case 0x1: /* ldub, load unsigned byte */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_UB);
> break;
> case 0x2: /* lduh, load unsigned halfword */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUW);
> break;
> case 0x3: /* ldd, load double word */
> if (rd & 1)
> @@ -5197,7 +5200,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>
> gen_address_mask(dc, cpu_addr);
> t64 = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_i64(t64, cpu_addr,
> + dc->mem_idx, MO_TEUQ);
> tcg_gen_trunc_i64_tl(cpu_val, t64);
> tcg_gen_ext32u_tl(cpu_val, cpu_val);
> gen_store_gpr(dc, rd + 1, cpu_val);
> @@ -5208,11 +5212,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> break;
> case 0x9: /* ldsb, load signed byte */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
> break;
> case 0xa: /* ldsh, load signed halfword */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TESW);
> break;
> case 0xd: /* ldstub */
> gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
> @@ -5266,11 +5271,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> #ifdef TARGET_SPARC64
> case 0x08: /* V9 ldsw */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TESL);
> break;
> case 0x0b: /* V9 ldx */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUQ);
> break;
> case 0x18: /* V9 ldswa */
> gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
> @@ -5369,15 +5376,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> switch (xop) {
> case 0x4: /* st, store word */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUL);
> break;
> case 0x5: /* stb, store byte */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
> break;
> case 0x6: /* sth, store halfword */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUW);
> break;
> case 0x7: /* std, store double word */
> if (rd & 1)
> @@ -5390,7 +5399,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> lo = gen_load_gpr(dc, rd + 1);
> t64 = tcg_temp_new_i64();
> tcg_gen_concat_tl_i64(t64, lo, cpu_val);
> - tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_i64(t64, cpu_addr,
> + dc->mem_idx, MO_TEUQ);
Should this be tcg_gen_qemu_st_tl() compared to the ones below? Or is there some
extra tidying up whereby _st64() is converted to _st_tl() in a #defined
TARGET_SPARC64 section?
> }
> break;
> #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
> @@ -5413,7 +5423,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> #ifdef TARGET_SPARC64
> case 0x0e: /* V9 stx */
> gen_address_mask(dc, cpu_addr);
> - tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
> + dc->mem_idx, MO_TEUQ);
> break;
> case 0x1e: /* V9 stxa */
> gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
> @@ -5438,11 +5449,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
> #ifdef TARGET_SPARC64
> gen_address_mask(dc, cpu_addr);
> if (rd == 1) {
> - tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
> + dc->mem_idx, MO_TEUQ);
> break;
> }
> #endif
> - tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
> + tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
> + dc->mem_idx, MO_TEUL);
Similar question here.
> }
> break;
> case 0x26:
ATB,
Mark.
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-03 20:11 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Mark Cave-Ayland
@ 2023-05-04 7:59 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-04 7:59 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, atar4qemu, jcmvbkbc
On 5/3/23 21:11, Mark Cave-Ayland wrote:
>> @@ -5390,7 +5399,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>> lo = gen_load_gpr(dc, rd + 1);
>> t64 = tcg_temp_new_i64();
>> tcg_gen_concat_tl_i64(t64, lo, cpu_val);
>> - tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
>> + tcg_gen_qemu_st_i64(t64, cpu_addr,
>> + dc->mem_idx, MO_TEUQ);
>
> Should this be tcg_gen_qemu_st_tl() compared to the ones below? Or is there some extra
> tidying up whereby _st64() is converted to _st_tl() in a #defined TARGET_SPARC64 section?
It's because we're using an explicit _i64 argument (t64),
so that we can store the pair for sparc32, where "tl" is _i32.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 8/9] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (6 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 7/9] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-02 14:11 ` Max Filippov
2023-05-02 13:57 ` [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-05 16:07 ` [PATCH 0/9] " Richard Henderson
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 0cf3075649..728aeebebf 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1549,7 +1549,7 @@ static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 res = tcg_temp_new_i32();
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
- tcg_gen_qemu_ld8u(res, addr, dc->cring);
+ tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB);
}
static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
@@ -1726,7 +1726,7 @@ static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
} else {
tmp = tcg_constant_i32(arg[1].imm);
}
- tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
+ tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL);
}
static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH 8/9] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*
2023-05-02 13:57 ` [PATCH 8/9] target/xtensa: " Richard Henderson
@ 2023-05-02 14:11 ` Max Filippov
0 siblings, 0 replies; 28+ messages in thread
From: Max Filippov @ 2023-05-02 14:11 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent,
philmd, jiaxun.yang, david, iii, thuth, mark.cave-ayland,
atar4qemu
On Tue, May 2, 2023 at 6:57 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Convert away from the old interface with the implicit
> MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/xtensa/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (7 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 8/9] target/xtensa: " Richard Henderson
@ 2023-05-02 13:57 ` Richard Henderson
2023-05-02 15:39 ` Taylor Simpson
2023-05-05 16:07 ` [PATCH 0/9] " Richard Henderson
9 siblings, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-05-02 13:57 UTC (permalink / raw)
To: qemu-devel
Cc: mrolnik, edgar.iglesias, tsimpson, ale, anjo, laurent, philmd,
jiaxun.yang, david, iii, thuth, mark.cave-ayland, atar4qemu,
jcmvbkbc
Remove the old interfaces with the implicit MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 55 --------------------------------------------
1 file changed, 55 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index dff17c7072..4401fa493c 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -841,61 +841,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp);
void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp);
-static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
-}
-
-static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
-}
-
-static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
-}
-
-static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
-}
-
-static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
-}
-
-static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
-}
-
-static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
-}
-
-static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
-}
-
-static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
-}
-
-static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
-}
-
-static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
-{
- tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
-}
-
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
TCGArg, MemOp);
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* RE: [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st
2023-05-02 13:57 ` [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
@ 2023-05-02 15:39 ` Taylor Simpson
2023-05-03 8:15 ` David Hildenbrand
0 siblings, 1 reply; 28+ messages in thread
From: Taylor Simpson @ 2023-05-02 15:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel@nongnu.org
Cc: mrolnik@gmail.com, edgar.iglesias@gmail.com, ale@rev.ng,
anjo@rev.ng, laurent@vivier.eu, philmd@linaro.org,
jiaxun.yang@flygoat.com, david@redhat.com, iii@linux.ibm.com,
thuth@redhat.com, mark.cave-ayland@ilande.co.uk,
atar4qemu@gmail.com, jcmvbkbc@gmail.com
> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, May 2, 2023 8:58 AM
> To: qemu-devel@nongnu.org
> Cc: mrolnik@gmail.com; edgar.iglesias@gmail.com; Taylor Simpson
> <tsimpson@quicinc.com>; ale@rev.ng; anjo@rev.ng; laurent@vivier.eu;
> philmd@linaro.org; jiaxun.yang@flygoat.com; david@redhat.com;
> iii@linux.ibm.com; thuth@redhat.com; mark.cave-ayland@ilande.co.uk;
> atar4qemu@gmail.com; jcmvbkbc@gmail.com
> Subject: [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st
>
> Remove the old interfaces with the implicit MemOp argument.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op.h | 55 --------------------------------------------
> 1 file changed, 55 deletions(-)
>
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index
> dff17c7072..4401fa493c 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -841,61 +841,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64, TCGv,
> TCGArg, MemOp); void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg,
> MemOp); void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp);
>
> -static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
> -}
> -
> -static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
> -}
> -
> -static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int
> mem_index) -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
> -}
> -
> -static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
> -}
> -
> -static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int
> mem_index) -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
> -}
> -
> -static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
> -}
> -
> -static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int
> mem_index) -{
> - tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
> -}
> -
> -static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) -
> {
> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
> -}
> -
> -static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
> -}
> -
> -static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
> -{
> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
> -}
> -
> -static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int
> mem_index) -{
> - tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
> -}
> -
> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
> TCGArg, MemOp); void
> tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
Is the intent that all loads use tcg_gen_qemu_ld_* and all stores use tcg_gen_qemu_st_*?
If so, there are other helpers to remove. For example,
tcg_gen_ld32u_i64
tcg_gen_st8_i64
Thanks,
Taylor
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st
2023-05-02 15:39 ` Taylor Simpson
@ 2023-05-03 8:15 ` David Hildenbrand
0 siblings, 0 replies; 28+ messages in thread
From: David Hildenbrand @ 2023-05-03 8:15 UTC (permalink / raw)
To: Taylor Simpson, Richard Henderson, qemu-devel@nongnu.org
Cc: mrolnik@gmail.com, edgar.iglesias@gmail.com, ale@rev.ng,
anjo@rev.ng, laurent@vivier.eu, philmd@linaro.org,
jiaxun.yang@flygoat.com, iii@linux.ibm.com, thuth@redhat.com,
mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com,
jcmvbkbc@gmail.com
On 02.05.23 17:39, Taylor Simpson wrote:
>
>
>> -----Original Message-----
>> From: Richard Henderson <richard.henderson@linaro.org>
>> Sent: Tuesday, May 2, 2023 8:58 AM
>> To: qemu-devel@nongnu.org
>> Cc: mrolnik@gmail.com; edgar.iglesias@gmail.com; Taylor Simpson
>> <tsimpson@quicinc.com>; ale@rev.ng; anjo@rev.ng; laurent@vivier.eu;
>> philmd@linaro.org; jiaxun.yang@flygoat.com; david@redhat.com;
>> iii@linux.ibm.com; thuth@redhat.com; mark.cave-ayland@ilande.co.uk;
>> atar4qemu@gmail.com; jcmvbkbc@gmail.com
>> Subject: [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st
>>
>> Remove the old interfaces with the implicit MemOp argument.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/tcg/tcg-op.h | 55 --------------------------------------------
>> 1 file changed, 55 deletions(-)
>>
>> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index
>> dff17c7072..4401fa493c 100644
>> --- a/include/tcg/tcg-op.h
>> +++ b/include/tcg/tcg-op.h
>> @@ -841,61 +841,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64, TCGv,
>> TCGArg, MemOp); void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg,
>> MemOp); void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp);
>>
>> -static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int
>> mem_index) -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int
>> mem_index) -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
>> -}
>> -
>> -static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int
>> mem_index) -{
>> - tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
>> -}
>> -
>> -static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) -
>> {
>> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
>> -}
>> -
>> -static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
>> -}
>> -
>> -static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
>> -{
>> - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
>> -}
>> -
>> -static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int
>> mem_index) -{
>> - tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
>> -}
>> -
>> void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
>> TCGArg, MemOp); void
>> tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
>
>
> Is the intent that all loads use tcg_gen_qemu_ld_* and all stores use tcg_gen_qemu_st_*?
>
> If so, there are other helpers to remove. For example,
> tcg_gen_ld32u_i64
> tcg_gen_st8_i64
At least the patch description + cover letter talks about "helpers for
qemu ld/st", so these two would not fall into the context of this patch
(and series).
Acked-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st
2023-05-02 13:57 [PATCH 0/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
` (8 preceding siblings ...)
2023-05-02 13:57 ` [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
@ 2023-05-05 16:07 ` Richard Henderson
9 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-05-05 16:07 UTC (permalink / raw)
To: qemu-devel
On 5/2/23 14:57, Richard Henderson wrote:
> Finishing this conversion has been a long time coming.
> This is a prerequisite to removing TARGET_ALIGNED_ONLY,
> which in turn is a prerequiste to building TCG once.
>
>
> r~
>
>
> Richard Henderson (9):
> target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/s390x: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/sparc: Finish conversion to tcg_gen_qemu_{ld,st}_*
> target/xtensa: Finish conversion to tcg_gen_qemu_{ld,st}_*
> tcg: Remove compatability helpers for qemu ld/st
Queued to tcg-next.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread