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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id r1sm3404590wrt.73.2020.07.08.22.11.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Jul 2020 22:11:10 -0700 (PDT) Subject: Re: [PATCH] cpu: Add starts_halted() method To: Eduardo Habkost References: <20200707204333.261506-1-bauerman@linux.ibm.com> <20200707214917.GX7276@habkost.net> <87y2nu3nxq.fsf@morokweng.localdomain> <20200708100038.GG18595@umbus.fritz.box> <20200708152540.GZ7276@habkost.net> <20200708213900.GD780932@habkost.net> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Autocrypt: addr=philmd@redhat.com; keydata= mQINBDXML8YBEADXCtUkDBKQvNsQA7sDpw6YLE/1tKHwm24A1au9Hfy/OFmkpzo+MD+dYc+7 bvnqWAeGweq2SDq8zbzFZ1gJBd6+e5v1a/UrTxvwBk51yEkadrpRbi+r2bDpTJwXc/uEtYAB GvsTZMtiQVA4kRID1KCdgLa3zztPLCj5H1VZhqZsiGvXa/nMIlhvacRXdbgllPPJ72cLUkXf z1Zu4AkEKpccZaJspmLWGSzGu6UTZ7UfVeR2Hcc2KI9oZB1qthmZ1+PZyGZ/Dy+z+zklC0xl XIpQPmnfy9+/1hj1LzJ+pe3HzEodtlVA+rdttSvA6nmHKIt8Ul6b/h1DFTmUT1lN1WbAGxmg CH1O26cz5nTrzdjoqC/b8PpZiT0kO5MKKgiu5S4PRIxW2+RA4H9nq7nztNZ1Y39bDpzwE5Sp bDHzd5owmLxMLZAINtCtQuRbSOcMjZlg4zohA9TQP9krGIk+qTR+H4CV22sWldSkVtsoTaA2 qNeSJhfHQY0TyQvFbqRsSNIe2gTDzzEQ8itsmdHHE/yzhcCVvlUzXhAT6pIN0OT+cdsTTfif MIcDboys92auTuJ7U+4jWF1+WUaJ8gDL69ThAsu7mGDBbm80P3vvUZ4fQM14NkxOnuGRrJxO qjWNJ2ZUxgyHAh5TCxMLKWZoL5hpnvx3dF3Ti9HW2dsUUWICSQARAQABtDJQaGlsaXBwZSBN YXRoaWV1LURhdWTDqSAoUGhpbCkgPHBoaWxtZEByZWRoYXQuY29tPokCVQQTAQgAPwIbDwYL CQgHAwIGFQgCCQoLBBYCAwECHgECF4AWIQSJweePYB7obIZ0lcuio/1u3q3A3gUCXsfWwAUJ KtymWgAKCRCio/1u3q3A3ircD/9Vjh3aFNJ3uF3hddeoFg1H038wZr/xi8/rX27M1Vj2j9VH 0B8Olp4KUQw/hyO6kUxqkoojmzRpmzvlpZ0cUiZJo2bQIWnvScyHxFCv33kHe+YEIqoJlaQc JfKYlbCoubz+02E2A6bFD9+BvCY0LBbEj5POwyKGiDMjHKCGuzSuDRbCn0Mz4kCa7nFMF5Jv piC+JemRdiBd6102ThqgIsyGEBXuf1sy0QIVyXgaqr9O2b/0VoXpQId7yY7OJuYYxs7kQoXI 6WzSMpmuXGkmfxOgbc/L6YbzB0JOriX0iRClxu4dEUg8Bs2pNnr6huY2Ft+qb41RzCJvvMyu gS32LfN0bTZ6Qm2A8ayMtUQgnwZDSO23OKgQWZVglGliY3ezHZ6lVwC24Vjkmq/2yBSLakZE 6DZUjZzCW1nvtRK05ebyK6tofRsx8xB8pL/kcBb9nCuh70aLR+5cmE41X4O+MVJbwfP5s/RW 9BFSL3qgXuXso/3XuWTQjJJGgKhB6xXjMmb1J4q/h5IuVV4juv1Fem9sfmyrh+Wi5V1IzKI7 RPJ3KVb937eBgSENk53P0gUorwzUcO+ASEo3Z1cBKkJSPigDbeEjVfXQMzNt0oDRzpQqH2vp apo2jHnidWt8BsckuWZpxcZ9+/9obQ55DyVQHGiTN39hkETy3Emdnz1JVHTU0Q== Message-ID: <714621e2-4585-e6ee-5812-f3a45aa09267@redhat.com> Date: Thu, 9 Jul 2020 07:11:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200708213900.GD780932@habkost.net> Content-Language: en-US Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=207.211.31.81; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/07 17:25:09 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , QEMU Developers , qemu-ppc , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Thiago Jung Bauermann , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/8/20 11:39 PM, Eduardo Habkost wrote: > On Wed, Jul 08, 2020 at 06:45:57PM +0200, Philippe Mathieu-Daudé wrote: >> On 7/8/20 5:25 PM, Eduardo Habkost wrote: >>> On Wed, Jul 08, 2020 at 02:14:03PM +0100, Peter Maydell wrote: >>>> On Wed, 8 Jul 2020 at 12:12, David Gibson wrote: >>>>> On Wed, Jul 08, 2020 at 10:38:29AM +0200, Philippe Mathieu-Daudé wrote: >>>>>> Class boolean field certainly sounds better, but I am not sure this >>>>>> is a property of the machine. Rather the arch? So move the field >>>>>> to CPUClass? Maybe not, let's discuss :) >>>>> >>>>> It is absolutely a property of the machine. e.g. I don't think we >>>>> want this for powernv. pseries is a bit of a special case since it is >>>>> explicitly a paravirt platform. But even for emulated hardware, the >>>>> board can absolutely strap things so that cpus do or don't start >>>>> immediately. >>>> >>>> It's a property of the individual CPU, I think. One common setup >>>> for Arm systems is that the primary CPU starts powered up but >>>> the secondaries all start powered down. >>> >>> Both statements can be true. It can be a property of the >>> individual CPU (although I'm not convinced it has to), but it >>> still needs to be controlled by the machine. >> >> From what said Peter, I understand this is a property of the >> chipset. Chipsets are modelled unevenly. >> >> IIUC QEMU started with single-core CPUs. >> CPUState had same meaning for 'core' or 'cpu', 1-1 mapping. >> >> Then multicore CPUs could be easily modelled using multiple >> single-core CPUs, usually created in the machine code. >> >> Then we moved to SoC models, creating the cores in the SoC. >> Some SoCs have array of cores, eventually heterogeneous >> (see the ZynqMP). We have containers of CPUState. >> >> On an ARM-based SoC, you might have the first core started >> (as said Peter) or not. >> >> BCM2836 / BCM2837 and ZynqMP start will all ARM cores off. >> On the BCM chipsets, a DSP core will boot the ARM cores. >> On the ZynqMP, a MicroBlaze core boots them. >> As QEMU doesn't models heterogeneous architectures, we start >> modelling after the unmodelled cores booted us, so either one >> or all cores on. >> >> In this case, we narrowed down the 'start-powered-off' field >> to the SoC, which happens to be how ARM SoCs are modelled. > > I was not aware of the start-powered-off property. If we make it > generic, we can just let spapr use it. > >> >> >> Chipsets providing a JTAG interface can have a SRST signal, >> the "system reset". When a JTAG probe is attached, it can >> keeps the whole chipset in a reset state. This is equivalent >> to QEMU '-S' mode (single step mode). >> >> >> I don't know about pseries hardware, but if this is 'explicit >> to paravirt platform', then I expect this to be the same with >> other accelerators/architectures. >> >> If paravirtualized -> cores start off by default. Let the >> hypervisor start them. So still a property of the CPUState >> depending on the accelerator used? > > I don't understand this part. Why would this depend on the > accelerator? Because starting a virtualized machine with all cores powered-off with TCG accelerator should at least emit a warning? Or change the behavior and start them powered-on? This is machine-specific although.