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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [Qemu-devel] [PATCH 2/2] target-ppc: fix interrupt vectors for
	MPC603 and e300
Date: Mon, 26 Apr 2010 17:02:39 +0200
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To: Alexander Graf <agraf@suse.de>
Cc: qemu-devel@nongnu.org

>> It is explained in [e300CORERM] at chapters 5.2.3, 5.5.1.1 and 8.3.3.
>> Clearly, the vector offset is 0x100 and the exception prefix can  
>> be 0 or
>> 0xFFF00000, depending of the MSR[IP] bit.
>>
>> So, yes, I'm sure the value of hreset_vector must be 0x100.
>> But hreset_excp_prefix can change. It could be another patch.
>
> Interesting. That's different from 970.

On 970, you can have the same effect (well, more general) by
changing HIOR.

>> About the prefix initialization, the datasheet says it is  
>> "determined by
>> MSR[IP]". and is "determined by the state of the msrip signal".  
>> But I don't
>> understand what is the msrip signal and how MSR[IP] is changed (is  
>> it related
>> to msrip ?). Do you have an explanation for this part ?

Your code can change MSR[IP]; there is also a strapping pin that is
sampled on HRESET (and copied to MSR[IP]).


Segher