From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com
Subject: Re: [PATCH v2 4/6] target/riscv: add support for zdinx
Date: Fri, 31 Dec 2021 12:07:55 -0800 [thread overview]
Message-ID: <71a505a1-fd9f-6cbd-2bbc-6bce301bf1f4@linaro.org> (raw)
In-Reply-To: <20211231032337.15579-5-liweiwei@iscas.ac.cn>
On 12/30/21 7:23 PM, Weiwei Li wrote:
> + if (reg_num != 0) {
> + switch (get_ol(ctx)) {
get_xl, not get_ol, two instances.
> +#ifdef TARGET_RISCV32
> + {
> + TCGv_i64 t = ftemp_new(ctx);
> + tcg_gen_concat_i32_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
> + return t;
> + }
> +#else
> + {
> + TCGv_i64 t = ftemp_new(ctx);
> + tcg_gen_deposit_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1], 32, 32);
> + return t;
> + }
Unify these two cases and use tcg_gen_concat_tl_i64.
r~
next prev parent reply other threads:[~2021-12-31 20:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-31 3:23 [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li
2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li
2021-12-31 6:28 ` Bin Meng
2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li
2021-12-31 19:56 ` Richard Henderson
2022-01-01 5:55 ` Weiwei Li
2022-01-01 19:46 ` Richard Henderson
2022-01-02 5:53 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li
2021-12-31 20:03 ` Richard Henderson
2021-12-31 20:06 ` Richard Henderson
2022-01-01 6:05 ` Weiwei Li
2022-01-01 19:48 ` Richard Henderson
2022-01-02 5:56 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li
2021-12-31 20:07 ` Richard Henderson [this message]
2022-01-01 6:06 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li
2021-12-31 20:08 ` Richard Henderson
2021-12-31 3:23 ` [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li
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