From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
To: "bmeng.cn@gmail.com" <bmeng.cn@gmail.com>
Cc: "bmeng@tinylab.org" <bmeng@tinylab.org>,
"bin.meng@windriver.com" <bin.meng@windriver.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check
Date: Mon, 5 Dec 2022 22:05:44 +0000 [thread overview]
Message-ID: <71b781e245b890e769c27fb37f7f380824bb239d.camel@wdc.com> (raw)
In-Reply-To: <CAEUhbmVO-OL9Awds3Q19gGhGC-agdq7JqxR28i3W+0CS0K76uw@mail.gmail.com>
On Mon, 2022-12-05 at 16:21 +0800, Bin Meng wrote:
> On Fri, Dec 2, 2022 at 8:28 AM Wilfred Mallawa
> <wilfred.mallawa@wdc.com> wrote:
> >
> > On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> > > The pending register upper limit is currently set to
> > > plic->num_sources >> 3, which is wrong, e.g.: considering
> > > plic->num_sources is 7, the upper limit becomes 0 which fails
> > > the range check if reading the pending register at pending_base.
> > >
> > > Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
> > > Signed-off-by: Bin Meng <bmeng@tinylab.org>
> > >
> > > ---
> > >
> > > hw/intc/sifive_plic.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> > > index 7a6a358c57..a3fc8222c7 100644
> > > --- a/hw/intc/sifive_plic.c
> > > +++ b/hw/intc/sifive_plic.c
> > > @@ -143,7 +143,8 @@ static uint64_t sifive_plic_read(void
> > > *opaque,
> > > hwaddr addr, unsigned size)
> > > uint32_t irq = (addr - plic->priority_base) >> 2;
> > >
> > > return plic->source_priority[irq];
> > > - } else if (addr_between(addr, plic->pending_base, plic-
> > > > num_sources >> 3)) {
> > > + } else if (addr_between(addr, plic->pending_base,
> > > + (plic->num_sources + 31) >> 3)) {
> > why does adding specifically 31 work here?
> >
>
> Each pending register is 32-bit for 32 interrupt sources. Adding 31
> is
> to round up to next pending register offset.
>
Ah I see, thanks for that.
Regards,
Wilfred
> Regards,
> Bin
next prev parent reply other threads:[~2022-12-05 22:06 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 14:07 [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-01 14:07 ` [PATCH 02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:07 ` [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-01 23:36 ` Wilfred Mallawa
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-04 22:24 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 05/15] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-01 23:39 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-01 23:57 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 4:21 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-07 4:28 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-02 0:03 ` Wilfred Mallawa
2022-12-07 4:30 ` Alistair Francis
2022-12-07 8:29 ` Conor Dooley
2022-12-01 14:08 ` [PATCH 10/15] hw/riscv: sifive_e: " Bin Meng
2022-12-02 0:05 ` Wilfred Mallawa
2022-12-07 4:31 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-02 0:06 ` Wilfred Mallawa
2022-12-07 4:33 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 4:35 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-07 4:36 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-02 0:11 ` Wilfred Mallawa
2022-12-07 4:37 ` Alistair Francis
2022-12-07 10:11 ` Bin Meng
2022-12-01 14:08 ` [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-02 0:27 ` Wilfred Mallawa
2022-12-05 8:21 ` Bin Meng
2022-12-05 22:05 ` Wilfred Mallawa [this message]
2022-12-07 5:08 ` Alistair Francis
2022-12-04 22:21 ` [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
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