From: Paolo Bonzini <pbonzini@redhat.com>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>, qemu-devel@nongnu.org
Cc: "Laurent Vivier" <lvivier@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Eduardo Habkost" <ehabkost@redhat.com>,
kvm@vger.kernel.org, "Michael S. Tsirkin" <mst@redhat.com>,
"Andrew Jeffery" <andrew@aj.id.au>,
"Jason Wang" <jasowang@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Joel Stanley" <joel@jms.id.au>,
qemu-trivial@nongnu.org, qemu-arm@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: Re: [PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
Date: Fri, 11 Sep 2020 09:28:34 +0200 [thread overview]
Message-ID: <71dad67c-a36e-8cd1-1f47-7a9bba1c74b0@redhat.com> (raw)
In-Reply-To: <20200910070131.435543-4-philmd@redhat.com>
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/dma/xilinx_axidma.c | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> index cf12a852ea1..19e14a2997e 100644
> --- a/hw/dma/xilinx_axidma.c
> +++ b/hw/dma/xilinx_axidma.c
> @@ -46,11 +46,11 @@
> OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
>
> #define XILINX_AXI_DMA_DATA_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> TYPE_XILINX_AXI_DMA_DATA_STREAM)
>
> #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
>
> #define R_DMACR (0x00 / 4)
> @@ -63,7 +63,7 @@
> #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
>
> typedef struct XilinxAXIDMA XilinxAXIDMA;
> -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
> +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
>
> enum {
> DMACR_RUNSTOP = 1,
> @@ -118,7 +118,7 @@ struct Stream {
> unsigned char txbuf[16 * 1024];
> };
>
> -struct XilinxAXIDMAStreamSlave {
> +struct XilinxAXIDMAStreamSink {
> Object parent;
>
> struct XilinxAXIDMA *dma;
> @@ -133,8 +133,8 @@ struct XilinxAXIDMA {
> uint32_t freqhz;
> StreamSink *tx_data_dev;
> StreamSink *tx_control_dev;
> - XilinxAXIDMAStreamSlave rx_data_dev;
> - XilinxAXIDMAStreamSlave rx_control_dev;
> + XilinxAXIDMAStreamSink rx_data_dev;
> + XilinxAXIDMAStreamSink rx_control_dev;
>
> struct Stream streams[2];
>
> @@ -390,7 +390,7 @@ static size_t
> xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> size_t len, bool eop)
> {
> - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> struct Stream *s = &cs->dma->streams[1];
>
> if (len != CONTROL_PAYLOAD_SIZE) {
> @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
> StreamCanPushNotifyFn notify,
> void *notify_opaque)
> {
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> struct Stream *s = &ds->dma->streams[1];
>
> if (!stream_running(s) || stream_idle(s)) {
> @@ -423,7 +423,7 @@ static size_t
> xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> bool eop)
> {
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> struct Stream *s = &ds->dma->streams[1];
> size_t ret;
>
> @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = {
> static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
> {
> XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> &s->rx_control_dev);
> int i;
>
> @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = {
> static const TypeInfo xilinx_axidma_data_stream_info = {
> .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_data_stream_class,
> .interfaces = (InterfaceInfo[]) {
> @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> static const TypeInfo xilinx_axidma_control_stream_info = {
> .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_control_stream_class,
> .interfaces = (InterfaceInfo[]) {
>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
next prev parent reply other threads:[~2020-09-11 7:29 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
2020-09-10 7:03 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 19:25 ` Cédric Le Goater
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
2020-09-10 7:06 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:30 ` Edgar E. Iglesias
2020-09-10 7:01 ` [PATCH 3/6] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini [this message]
2020-09-11 7:31 ` Edgar E. Iglesias
2020-09-10 7:01 ` [PATCH 4/6] hw/net/xilinx_axienet: " Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:32 ` Edgar E. Iglesias
2020-09-10 7:01 ` [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' Philippe Mathieu-Daudé
2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:30 ` Philippe Mathieu-Daudé
2020-09-10 9:11 ` Paolo Bonzini
2020-09-10 9:14 ` Daniel P. Berrangé
2020-09-10 11:36 ` Paolo Bonzini
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
2020-09-10 7:08 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 10:13 ` Laurent Vivier
2020-09-10 7:38 ` [PATCH 0/6] misc: Some inclusive terminology changes Laurent Vivier
2020-09-17 19:02 ` Laurent Vivier
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