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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id e2-20020a9d63c2000000b006b8850ad193sm6987468otl.56.2023.07.05.10.04.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Jul 2023 10:04:22 -0700 (PDT) Message-ID: <71ebf920-3614-b19d-1623-1dee4a9d716e@gmail.com> Date: Wed, 5 Jul 2023 14:04:17 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] pnv/xive: Print CPU target in all TIMA traces Content-Language: en-US To: Frederic Barrat , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20230705110039.231148-1-fbarrat@linux.ibm.com> From: Daniel Henrique Barboza In-Reply-To: <20230705110039.231148-1-fbarrat@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/5/23 08:00, Frederic Barrat wrote: > Add the CPU target in the trace when reading/writing the TIMA > space. It was already done for other TIMA ops (notify, accept, ...), > only missing for those 2. Useful for debug and even more now that we > experiment with SMT. > > Signed-off-by: Frederic Barrat > --- > hw/intc/trace-events | 4 ++-- > hw/intc/xive.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/trace-events b/hw/intc/trace-events > index 5c6094c457..36ff71f947 100644 > --- a/hw/intc/trace-events > +++ b/hw/intc/trace-events > @@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64 > xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value) "@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64 > xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data) "END 0x%02x/0x%04x -> enqueue 0x%08x" > xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk, uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END 0x%02x/0x%04x data 0x%08x" > -xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64 > -xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value) "@0x%"PRIx64" sz=%d val=0x%" PRIx64 > +xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 > +xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64 > xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found NVT 0x%x/0x%x ring=0x%x" > xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64 > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index c014e961a4..56670b2cac 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -566,7 +566,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, > { > const XiveTmOp *xto; > > - trace_xive_tctx_tm_write(offset, size, value); > + trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); > > /* > * TODO: check V bit in Q[0-3]W2 > @@ -639,7 +639,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, > */ > ret = xive_tm_raw_read(tctx, offset, size); > out: > - trace_xive_tctx_tm_read(offset, size, ret); > + trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret); > return ret; > } >