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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id l62sm2171616edl.89.2020.03.31.00.52.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Mar 2020 00:52:01 -0700 (PDT) Subject: Re: [PATCH v1] usb: Add read support for HCIVERSION register to XHCI To: Cameron Esfahani , qemu-devel@nongnu.org References: <20200330214444.43494-1-dirty@apple.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <71ec6105-b2f7-4805-c235-645c25a0b201@redhat.com> Date: Tue, 31 Mar 2020 09:52:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200330214444.43494-1-dirty@apple.com> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Mustacchi , Paolo Bonzini , kraxel@redhat.com, Paul Menzel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/30/20 11:44 PM, Cameron Esfahani via wrote: > macOS will read HCIVERSION separate from CAPLENGTH. Add a distinct > handler for that register. Apparently a fix for https://bugs.launchpad.net/qemu/+bug/1693050. > > Signed-off-by: Cameron Esfahani > --- > hw/usb/hcd-xhci.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c > index b330e36fe6..061f8438de 100644 > --- a/hw/usb/hcd-xhci.c > +++ b/hw/usb/hcd-xhci.c > @@ -2739,6 +2739,9 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) > case 0x00: /* HCIVERSION, CAPLENGTH */ > ret = 0x01000000 | LEN_CAP; > break; > + case 0x02: /* HCIVERSION */ > + ret = 0x0100; > + break; But we have: static const MemoryRegionOps xhci_cap_ops = { .read = xhci_cap_read, .write = xhci_cap_write, .valid.min_access_size = 1, .valid.max_access_size = 4, .impl.min_access_size = 4, .impl.max_access_size = 4, .endianness = DEVICE_LITTLE_ENDIAN, }; IIUC ".impl.min_access_size = 4" means the case 'reg == 2' can not happen. It seems we have a bug in memory.c elsewhere. How can we reproduce? If not easy, can you share the backtrace of: -- >8 -- diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index b330e36fe6..d021129f3f 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2735,6 +2735,7 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) XHCIState *xhci = ptr; uint32_t ret; + assert(reg != 2); switch (reg) { case 0x00: /* HCIVERSION, CAPLENGTH */ ret = 0x01000000 | LEN_CAP; --- > case 0x04: /* HCSPARAMS 1 */ > ret = ((xhci->numports_2+xhci->numports_3)<<24) > | (xhci->numintrs<<8) | xhci->numslots; >