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([2001:b07:6468:f312:9af8:e5f5:7516:fa89]) by smtp.googlemail.com with ESMTPSA id bo6-20020a170906d04600b008eb5877a221sm4619137ejb.75.2023.03.06.06.10.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Mar 2023 06:10:38 -0800 (PST) Message-ID: <71ed58bd-fb24-4eab-6638-a6a88676201b@redhat.com> Date: Mon, 6 Mar 2023 15:10:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH 4/8] edu: add smp_mb__after_rmw() Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, gshan@redhat.com, eesposit@redhat.com, david@redhat.com, stefanha@redhat.com, cohuck@redhat.com, eauger@redhat.com References: <20230303171939.237819-1-pbonzini@redhat.com> <20230303171939.237819-5-pbonzini@redhat.com> From: Paolo Bonzini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/6/23 14:38, Peter Maydell wrote: > On Fri, 3 Mar 2023 at 17:21, Paolo Bonzini wrote: >> >> Ensure ordering between clearing the COMPUTING flag and checking >> IRQFACT, and between setting the IRQFACT flag and checking >> COMPUTING. This ensures that no wakeups are lost. >> >> Signed-off-by: Paolo Bonzini > > Why is this device even messing around with multiple > threads and atomics anyway ?? Because it is an example of deferring device work to another thread, just like on real hardware it may be deferred to an on-device microcontroller or CPU. In particular, in this case I think it is useful to show a pitfall that is present in emulated hardware (where all loads and stores ultimately go through a store buffer and CPU cache) and not in real hardware (where I/O registers are always uncached). > I'm quite tempted to suggest we should deprecate-and-drop > this; it's not real hardware, it doesn't do anything > useful, and it's not a good model to follow if you're > implementing some other device. I'm okay with deprecating it but I think it has educational value. Paolo