From: Paolo Bonzini <pbonzini@redhat.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>,
Gerd Hoffmann <kraxel@redhat.com>,
qemu-devel@nongnu.org
Cc: Marcelo Tosatti <mtosatti@redhat.com>, kvm@vger.kernel.org
Subject: Re: [PATCH 1/1] kvm: add support for guest physical bits
Date: Wed, 6 Mar 2024 23:50:24 +0100 [thread overview]
Message-ID: <71f2c072-b25b-4980-938e-d832740cbefa@redhat.com> (raw)
In-Reply-To: <3ab64c0f-7387-4738-b78c-cf798528d5f4@intel.com>
On 3/4/24 02:54, Xiaoyao Li wrote:
> On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
>> query kvm for supported guest physical address bits using
>> KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
>> (leaf 0x80000008, eax, bits 16-23).
>>
>> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
>> ---
>> target/i386/cpu.h | 1 +
>> target/i386/cpu.c | 1 +
>> target/i386/kvm/kvm.c | 8 ++++++++
>> 3 files changed, 10 insertions(+)
>>
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 952174bb6f52..d427218827f6 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -2026,6 +2026,7 @@ struct ArchCPU {
>> /* Number of physical address bits supported */
>> uint32_t phys_bits;
>> + uint32_t guest_phys_bits;
>> /* in order to simplify APIC support, we leave this pointer to the
>> user */
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 2666ef380891..1a6cfc75951e 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t
>> index, uint32_t count,
>> if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
>> /* 64 bit processor */
>> *eax |= (cpu_x86_virtual_addr_width(env) << 8);
>> + *eax |= (cpu->guest_phys_bits << 16);
>
> I think you misunderstand this field.
>
> If you expose this field to guest, it's the information for nested
> guest. i.e., the guest itself runs as a hypervisor will know its nested
> guest can have guest_phys_bits for physical addr.
It's one possible interpretation of AMD's definition. However there's no
processor that has different MAXPHYADDR with/without nested paging, so
there's no real benefit in adopting that interpretation.
The only architectural case in which you have two conflicting values for
the guest MAXPHYADDR is hCR4.LA57=0 (and likewise for Intel 4-level EPT)
with MAXPHYADDR=52, so it's useful to treat GuestPhysAddrSize as a way
to communicate this situation to the guest.
Paolo
prev parent reply other threads:[~2024-03-06 22:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-01 10:17 [PATCH 0/1] kvm: add support for guest physical bits Gerd Hoffmann
2024-03-01 10:17 ` [PATCH 1/1] " Gerd Hoffmann
2024-03-04 1:54 ` Xiaoyao Li
2024-03-04 4:05 ` Tao Su
2024-03-04 14:58 ` Gerd Hoffmann
2024-03-05 3:03 ` Xiaoyao Li
2024-03-06 22:50 ` Paolo Bonzini [this message]
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