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[176.171.219.76]) by smtp.gmail.com with ESMTPSA id r9-20020a05600c320900b0040644e699a0sm19205355wmp.45.2023.10.25.06.01.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Oct 2023 06:01:14 -0700 (PDT) Message-ID: <721493f2-fe31-548e-83e8-d8d6bd3a53df@linaro.org> Date: Wed, 25 Oct 2023 15:01:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Content-Language: en-US To: qemu-devel@nongnu.org Cc: Joel Stanley , Peter Maydell , Andrew Jeffery , qemu-arm@nongnu.org, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= References: <20231024162423.40206-1-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20231024162423.40206-1-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.339, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 24/10/23 18:24, Philippe Mathieu-Daudé wrote: > Philippe Mathieu-Daudé (11): > hw/arm/aspeed: Extract code common to all boards to a common file > hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific > hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific > hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field > hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC > hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC > hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC > hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize > hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState > hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState > hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState Updating other reviewers, this series has been queued in Cédric's ASPEED queue.