* [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max
@ 2024-06-21 14:39 Gustavo Romero
2024-06-21 14:39 ` [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Gustavo Romero
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Gustavo Romero @ 2024-06-21 14:39 UTC (permalink / raw)
To: qemu-devel, alex.bennee, richard.henderson
Cc: philmd, peter.maydell, gustavo.romero
Enable FEAT_Debugv8p8 on Arm max CPU.
v2:
- Revert to the original comment above call to aa32_max_features()
Gustavo Romero (2):
target/arm: Move initialization of debug ID registers
target/arm: Enable FEAT_Debugv8p8 for -cpu max
target/arm/cpu.h | 2 ++
target/arm/tcg/cpu32.c | 34 +++++++++++++++++++++++++++++-----
target/arm/tcg/cpu64.c | 4 ++--
3 files changed, 33 insertions(+), 7 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/2] target/arm: Move initialization of debug ID registers 2024-06-21 14:39 [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero @ 2024-06-21 14:39 ` Gustavo Romero 2024-06-24 13:26 ` Peter Maydell 2024-06-21 14:39 ` [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero 2024-06-21 16:50 ` [PATCH v2 0/2] " Richard Henderson 2 siblings, 1 reply; 8+ messages in thread From: Gustavo Romero @ 2024-06-21 14:39 UTC (permalink / raw) To: qemu-devel, alex.bennee, richard.henderson Cc: philmd, peter.maydell, gustavo.romero Move the initialization of the debug ID registers to aa32_max_features, which is used to set the 32-bit ID registers. This ensures that the debug ID registers are consistently set for the max CPU in a single place. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> --- target/arm/cpu.h | 2 ++ target/arm/tcg/cpu32.c | 30 +++++++++++++++++++++++++++--- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3841359d0f..d8eb986a04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4) FIELD(DBGDEVID, AUXREGS, 24, 4) FIELD(DBGDEVID, CIDMASK, 28, 4) +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) + FIELD(MVFR0, SIMDREG, 0, 4) FIELD(MVFR0, FPSP, 4, 4) FIELD(MVFR0, FPDP, 8, 4) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bdd82d912a..b155a0136f 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -87,6 +87,33 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t = 0x00008000; + t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t = FIELD_DP32(t, DBGDIDR, BRPS, 5); + t = FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr = t; + + t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid = t; + + /* Bits[31:4] are RES0. */ + t = 0; + t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 = t; + t = cpu->isar.id_dfr1; t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_dfr1 = t; @@ -955,9 +982,6 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar4 = 0x00011142; cpu->isar.id_isar5 = 0x00011121; cpu->isar.id_isar6 = 0; - cpu->isar.dbgdidr = 0x3516d000; - cpu->isar.dbgdevid = 0x00110f13; - cpu->isar.dbgdevid1 = 0x2; cpu->isar.reset_pmcr_el0 = 0x41013000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0899251eef..71e1bfcd4e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,7 +1167,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar2; t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ + t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ cpu->isar.id_aa64isar2 = t; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers 2024-06-21 14:39 ` [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Gustavo Romero @ 2024-06-24 13:26 ` Peter Maydell 2024-06-24 18:13 ` Gustavo Romero 0 siblings, 1 reply; 8+ messages in thread From: Peter Maydell @ 2024-06-24 13:26 UTC (permalink / raw) To: Gustavo Romero; +Cc: qemu-devel, alex.bennee, richard.henderson, philmd On Fri, 21 Jun 2024 at 15:39, Gustavo Romero <gustavo.romero@linaro.org> wrote: > > Move the initialization of the debug ID registers to aa32_max_features, > which is used to set the 32-bit ID registers. This ensures that the > debug ID registers are consistently set for the max CPU in a single > place. > > Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> > --- > target/arm/cpu.h | 2 ++ > target/arm/tcg/cpu32.c | 30 +++++++++++++++++++++++++++--- > target/arm/tcg/cpu64.c | 2 +- > 3 files changed, 30 insertions(+), 4 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 3841359d0f..d8eb986a04 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4) > FIELD(DBGDEVID, AUXREGS, 24, 4) > FIELD(DBGDEVID, CIDMASK, 28, 4) > > +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) > + > FIELD(MVFR0, SIMDREG, 0, 4) > FIELD(MVFR0, FPSP, 4, 4) > FIELD(MVFR0, FPDP, 8, 4) > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index bdd82d912a..b155a0136f 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -87,6 +87,33 @@ void aa32_max_features(ARMCPU *cpu) > t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ > cpu->isar.id_dfr0 = t; > > + /* Debug ID registers. */ > + > + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ > + t = 0x00008000; > + t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); > + t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); > + t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ > + t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); > + t = FIELD_DP32(t, DBGDIDR, BRPS, 5); > + t = FIELD_DP32(t, DBGDIDR, WRPS, 3); > + cpu->isar.dbgdidr = t; > + > + t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); Looks like we should have an initial "t = something" ("t = 0") before this line? Otherwise we start the DBGDEVID value with the value of DBGDIDR. > + t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); > + t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); > + t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); > + t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); > + t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); > + t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); > + t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); > + cpu->isar.dbgdevid = t; > + > + /* Bits[31:4] are RES0. */ > + t = 0; > + t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); > + cpu->isar.dbgdevid1 = t; > + > t = cpu->isar.id_dfr1; > t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ > cpu->isar.id_dfr1 = t; > @@ -955,9 +982,6 @@ static void arm_max_initfn(Object *obj) > cpu->isar.id_isar4 = 0x00011142; > cpu->isar.id_isar5 = 0x00011121; > cpu->isar.id_isar6 = 0; > - cpu->isar.dbgdidr = 0x3516d000; > - cpu->isar.dbgdevid = 0x00110f13; > - cpu->isar.dbgdevid1 = 0x2; > cpu->isar.reset_pmcr_el0 = 0x41013000; > cpu->clidr = 0x0a200023; > cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 0899251eef..71e1bfcd4e 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1167,7 +1167,7 @@ void aarch64_max_tcg_initfn(Object *obj) > > t = cpu->isar.id_aa64isar2; > t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ > - t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ > + t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ > t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ > cpu->isar.id_aa64isar2 = t; This indent fixup is unrelated so should really be its own patch. thanks -- PMM ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers 2024-06-24 13:26 ` Peter Maydell @ 2024-06-24 18:13 ` Gustavo Romero 0 siblings, 0 replies; 8+ messages in thread From: Gustavo Romero @ 2024-06-24 18:13 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, alex.bennee, richard.henderson, philmd Hi Peter! On 6/24/24 10:26 AM, Peter Maydell wrote: > On Fri, 21 Jun 2024 at 15:39, Gustavo Romero <gustavo.romero@linaro.org> wrote: >> >> Move the initialization of the debug ID registers to aa32_max_features, >> which is used to set the 32-bit ID registers. This ensures that the >> debug ID registers are consistently set for the max CPU in a single >> place. >> >> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> >> --- >> target/arm/cpu.h | 2 ++ >> target/arm/tcg/cpu32.c | 30 +++++++++++++++++++++++++++--- >> target/arm/tcg/cpu64.c | 2 +- >> 3 files changed, 30 insertions(+), 4 deletions(-) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index 3841359d0f..d8eb986a04 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4) >> FIELD(DBGDEVID, AUXREGS, 24, 4) >> FIELD(DBGDEVID, CIDMASK, 28, 4) >> >> +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) >> + >> FIELD(MVFR0, SIMDREG, 0, 4) >> FIELD(MVFR0, FPSP, 4, 4) >> FIELD(MVFR0, FPDP, 8, 4) >> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c >> index bdd82d912a..b155a0136f 100644 >> --- a/target/arm/tcg/cpu32.c >> +++ b/target/arm/tcg/cpu32.c >> @@ -87,6 +87,33 @@ void aa32_max_features(ARMCPU *cpu) >> t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ >> cpu->isar.id_dfr0 = t; >> >> + /* Debug ID registers. */ >> + >> + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ >> + t = 0x00008000; >> + t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); >> + t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); >> + t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ >> + t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); >> + t = FIELD_DP32(t, DBGDIDR, BRPS, 5); >> + t = FIELD_DP32(t, DBGDIDR, WRPS, 3); >> + cpu->isar.dbgdidr = t; >> + >> + t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); > > Looks like we should have an initial "t = something" ("t = 0") > before this line? Otherwise we start the DBGDEVID value > with the value of DBGDIDR. I'm setting all the 32 bits here so there is no bit left from previous t value. But I agree it's better to be explicit here for readability. Done in v3. >> + t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); >> + t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); >> + t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); >> + t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); >> + t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); >> + t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); >> + t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); >> + cpu->isar.dbgdevid = t; >> + >> + /* Bits[31:4] are RES0. */ >> + t = 0; >> + t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); >> + cpu->isar.dbgdevid1 = t; >> + >> t = cpu->isar.id_dfr1; >> t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ >> cpu->isar.id_dfr1 = t; >> @@ -955,9 +982,6 @@ static void arm_max_initfn(Object *obj) >> cpu->isar.id_isar4 = 0x00011142; >> cpu->isar.id_isar5 = 0x00011121; >> cpu->isar.id_isar6 = 0; >> - cpu->isar.dbgdidr = 0x3516d000; >> - cpu->isar.dbgdevid = 0x00110f13; >> - cpu->isar.dbgdevid1 = 0x2; >> cpu->isar.reset_pmcr_el0 = 0x41013000; >> cpu->clidr = 0x0a200023; >> cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ >> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c >> index 0899251eef..71e1bfcd4e 100644 >> --- a/target/arm/tcg/cpu64.c >> +++ b/target/arm/tcg/cpu64.c >> @@ -1167,7 +1167,7 @@ void aarch64_max_tcg_initfn(Object *obj) >> >> t = cpu->isar.id_aa64isar2; >> t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ >> - t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ >> + t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ >> t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ >> cpu->isar.id_aa64isar2 = t; > > This indent fixup is unrelated so should really be its own patch. Got it. Done in v3 so. Cheers, Gustavo ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max 2024-06-21 14:39 [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero 2024-06-21 14:39 ` [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Gustavo Romero @ 2024-06-21 14:39 ` Gustavo Romero 2024-06-24 13:27 ` Peter Maydell 2024-06-21 16:50 ` [PATCH v2 0/2] " Richard Henderson 2 siblings, 1 reply; 8+ messages in thread From: Gustavo Romero @ 2024-06-21 14:39 UTC (permalink / raw) To: qemu-devel, alex.bennee, richard.henderson Cc: philmd, peter.maydell, gustavo.romero Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is reported as supported in the ID registers. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> --- target/arm/tcg/cpu32.c | 6 +++--- target/arm/tcg/cpu64.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index b155a0136f..a1273a73a3 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 = t; t = cpu->isar.id_dfr0; - t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) t = 0x00008000; t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); t = FIELD_DP32(t, DBGDIDR, BRPS, 5); t = FIELD_DP32(t, DBGDIDR, WRPS, 3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 71e1bfcd4e..fe232eb306 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->isar.id_aa64zfr0 = t; t = cpu->isar.id_aa64dfr0; - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_aa64dfr0 = t; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max 2024-06-21 14:39 ` [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero @ 2024-06-24 13:27 ` Peter Maydell 2024-06-24 18:14 ` Gustavo Romero 0 siblings, 1 reply; 8+ messages in thread From: Peter Maydell @ 2024-06-24 13:27 UTC (permalink / raw) To: Gustavo Romero; +Cc: qemu-devel, alex.bennee, richard.henderson, philmd On Fri, 21 Jun 2024 at 15:39, Gustavo Romero <gustavo.romero@linaro.org> wrote: > > Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU > since it concerns the external debug interface for JTAG, but is > mandatory in Armv8.8 implementations, hence it is reported as supported > in the ID registers. > > Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> > --- > target/arm/tcg/cpu32.c | 6 +++--- > target/arm/tcg/cpu64.c | 2 +- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c > index b155a0136f..a1273a73a3 100644 > --- a/target/arm/tcg/cpu32.c > +++ b/target/arm/tcg/cpu32.c > @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) > cpu->isar.id_pfr2 = t; > > t = cpu->isar.id_dfr0; > - t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ > - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ > + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ > + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ > t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ > cpu->isar.id_dfr0 = t; > > @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) > t = 0x00008000; > t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); > t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); > - t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ > + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ > t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); > t = FIELD_DP32(t, DBGDIDR, BRPS, 5); > t = FIELD_DP32(t, DBGDIDR, WRPS, 3); > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 71e1bfcd4e..fe232eb306 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) > cpu->isar.id_aa64zfr0 = t; > > t = cpu->isar.id_aa64dfr0; > - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ > + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ > t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ > t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ > cpu->isar.id_aa64dfr0 = t; > -- We also need to add Feat_Debugv8p8 to the (alphabetically-sorted) list of emulated features in docs/system/arm/emulation.rst. thanks -- PMM ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max 2024-06-24 13:27 ` Peter Maydell @ 2024-06-24 18:14 ` Gustavo Romero 0 siblings, 0 replies; 8+ messages in thread From: Gustavo Romero @ 2024-06-24 18:14 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, alex.bennee, richard.henderson, philmd Hi Peter, On 6/24/24 10:27 AM, Peter Maydell wrote: > On Fri, 21 Jun 2024 at 15:39, Gustavo Romero <gustavo.romero@linaro.org> wrote: >> >> Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU >> since it concerns the external debug interface for JTAG, but is >> mandatory in Armv8.8 implementations, hence it is reported as supported >> in the ID registers. >> >> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> >> --- >> target/arm/tcg/cpu32.c | 6 +++--- >> target/arm/tcg/cpu64.c | 2 +- >> 2 files changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c >> index b155a0136f..a1273a73a3 100644 >> --- a/target/arm/tcg/cpu32.c >> +++ b/target/arm/tcg/cpu32.c >> @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) >> cpu->isar.id_pfr2 = t; >> >> t = cpu->isar.id_dfr0; >> - t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ >> - t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ >> + t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ >> + t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ >> cpu->isar.id_dfr0 = t; >> >> @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) >> t = 0x00008000; >> t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); >> t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); >> - t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ >> + t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); >> t = FIELD_DP32(t, DBGDIDR, BRPS, 5); >> t = FIELD_DP32(t, DBGDIDR, WRPS, 3); >> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c >> index 71e1bfcd4e..fe232eb306 100644 >> --- a/target/arm/tcg/cpu64.c >> +++ b/target/arm/tcg/cpu64.c >> @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) >> cpu->isar.id_aa64zfr0 = t; >> >> t = cpu->isar.id_aa64dfr0; >> - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ >> + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ >> t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ >> t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ >> cpu->isar.id_aa64dfr0 = t; >> -- > > We also need to add Feat_Debugv8p8 to the (alphabetically-sorted) > list of emulated features in docs/system/arm/emulation.rst. oh, I forgot it. Thanks, done in v3. Cheers, Gustavo ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max 2024-06-21 14:39 [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero 2024-06-21 14:39 ` [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Gustavo Romero 2024-06-21 14:39 ` [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero @ 2024-06-21 16:50 ` Richard Henderson 2 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2024-06-21 16:50 UTC (permalink / raw) To: Gustavo Romero, qemu-devel, alex.bennee; +Cc: philmd, peter.maydell On 6/21/24 07:39, Gustavo Romero wrote: > Gustavo Romero (2): > target/arm: Move initialization of debug ID registers > target/arm: Enable FEAT_Debugv8p8 for -cpu max Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-06-24 18:15 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-21 14:39 [PATCH v2 0/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero 2024-06-21 14:39 ` [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Gustavo Romero 2024-06-24 13:26 ` Peter Maydell 2024-06-24 18:13 ` Gustavo Romero 2024-06-21 14:39 ` [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Gustavo Romero 2024-06-24 13:27 ` Peter Maydell 2024-06-24 18:14 ` Gustavo Romero 2024-06-21 16:50 ` [PATCH v2 0/2] " Richard Henderson
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