From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Alistair Francis <alistair23@gmail.com>, qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL v2 00/27] riscv-to-apply queue
Date: Mon, 3 Jun 2024 14:51:28 +0200 [thread overview]
Message-ID: <72f7fe62-5561-4f2f-a23f-f21bd65c0921@linaro.org> (raw)
In-Reply-To: <20240603111643.258712-1-alistair.francis@wdc.com>
Hi Alistair,
On 3/6/24 13:16, Alistair Francis wrote:
> The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184:
>
> Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603
>
> for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de:
>
> disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.1
>
> * APLICs add child earlier than realize
> * Fix exposure of Zkr
> * Raise exceptions on wrs.nto
> * Implement SBI debug console (DBCN) calls for KVM
> * Support 64-bit addresses for initrd
> * Change RISCV_EXCP_SEMIHOST exception number to 63
> * Tolerate KVM disable ext errors
> * Set tval in breakpoints
> * Add support for Zve32x extension
> * Add support for Zve64x extension
> * Relax vector register check in RISCV gdbstub
> * Fix the element agnostic Vector function problem
> * Fix Zvkb extension config
> * Implement dynamic establishment of custom decoder
> * Add th.sxstatus CSR emulation
> * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
> * Check single width operator for vector fp widen instructions
> * Check single width operator for vfncvt.rod.f.f.w
> * Remove redudant SEW checking for vector fp narrow/widen instructions
> * Prioritize pmp errors in raise_mmu_exception()
> * Do not set mtval2 for non guest-page faults
> * Remove experimental prefix from "B" extension
> * Fixup CBO extension register calculation
> * Fix the hart bit setting of AIA
> * Fix reg_width in ricsv_gen_dynamic_vector_feature()
> * Decode all of the pmpcfg and pmpaddr CSRs
>
> ----------------------------------------------------------------
Please have a look at this bugfix:
https://lore.kernel.org/qemu-devel/20240419110514.69697-1-philmd@linaro.org/
next prev parent reply other threads:[~2024-06-03 12:51 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 11:16 [PULL v2 00/27] riscv-to-apply queue Alistair Francis
2024-06-03 11:16 ` [PULL v2 01/27] hw/intc/riscv_aplic: APLICs should add child earlier than realize Alistair Francis
2024-06-03 11:16 ` [PULL v2 02/27] target/riscv/kvm: Fix exposure of Zkr Alistair Francis
2024-06-03 11:16 ` [PULL v2 03/27] target/riscv: Raise exceptions on wrs.nto Alistair Francis
2024-06-03 11:16 ` [PULL v2 04/27] target/riscv/kvm: implement SBI debug console (DBCN) calls Alistair Francis
2024-06-03 11:16 ` [PULL v2 05/27] hw/riscv/boot.c: Support 64-bit address for initrd Alistair Francis
2024-06-03 11:16 ` [PULL v2 06/27] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 Alistair Francis
2024-06-03 11:16 ` [PULL v2 07/27] target/riscv/kvm: tolerate KVM disable ext errors Alistair Francis
2024-06-03 11:16 ` [PULL v2 08/27] target/riscv/debug: set tval=pc in breakpoint exceptions Alistair Francis
2024-06-03 11:16 ` [PULL v2 09/27] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint Alistair Francis
2024-06-03 11:16 ` [PULL v2 10/27] target/riscv: Add support for Zve32x extension Alistair Francis
2024-06-03 11:16 ` [PULL v2 11/27] target/riscv: Add support for Zve64x extension Alistair Francis
2024-06-03 11:16 ` [PULL v2 12/27] target/riscv: Relax vector register check in RISCV gdbstub Alistair Francis
2024-06-03 11:16 ` [PULL v2 13/27] target/riscv: Fix the element agnostic function problem Alistair Francis
2024-06-03 11:16 ` [PULL v2 14/27] target/riscv/cpu.c: fix Zvkb extension config Alistair Francis
2024-06-03 11:16 ` [PULL v2 15/27] target/riscv: Implement dynamic establishment of custom decoder Alistair Francis
2024-06-03 11:16 ` [PULL v2 16/27] riscv: thead: Add th.sxstatus CSR emulation Alistair Francis
2024-06-03 11:16 ` [PULL v2 17/27] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Alistair Francis
2024-06-03 11:16 ` [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions Alistair Francis
2024-06-03 11:16 ` [PULL v2 19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Alistair Francis
2024-06-03 11:16 ` [PULL v2 20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Alistair Francis
2024-06-03 11:16 ` [PULL v2 21/27] target/riscv: prioritize pmp errors in raise_mmu_exception() Alistair Francis
2024-06-03 11:16 ` [PULL v2 22/27] target/riscv: do not set mtval2 for non guest-page faults Alistair Francis
2024-06-03 11:16 ` [PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extension Alistair Francis
2024-06-03 11:16 ` [PULL v2 24/27] target/riscv: rvzicbo: Fixup CBO extension register calculation Alistair Francis
2024-06-03 11:16 ` [PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA Alistair Francis
2024-06-03 11:16 ` [PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() Alistair Francis
2024-06-03 11:16 ` [PULL v2 27/27] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs Alistair Francis
2024-06-03 12:51 ` Philippe Mathieu-Daudé [this message]
2024-06-04 10:22 ` [PULL v2 00/27] riscv-to-apply queue Richard Henderson
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