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Mon, 03 Jun 2024 05:51:30 -0700 (PDT) Message-ID: <72f7fe62-5561-4f2f-a23f-f21bd65c0921@linaro.org> Date: Mon, 3 Jun 2024 14:51:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PULL v2 00/27] riscv-to-apply queue To: Alistair Francis , qemu-devel@nongnu.org Cc: Alistair Francis References: <20240603111643.258712-1-alistair.francis@wdc.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240603111643.258712-1-alistair.francis@wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Alistair, On 3/6/24 13:16, Alistair Francis wrote: > The following changes since commit 74abb45dac6979e7ff76172b7f0a24e869405184: > > Merge tag 'pull-target-arm-20240531' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-05-31 11:10:10 -0700) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240603 > > for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de: > > disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.1 > > * APLICs add child earlier than realize > * Fix exposure of Zkr > * Raise exceptions on wrs.nto > * Implement SBI debug console (DBCN) calls for KVM > * Support 64-bit addresses for initrd > * Change RISCV_EXCP_SEMIHOST exception number to 63 > * Tolerate KVM disable ext errors > * Set tval in breakpoints > * Add support for Zve32x extension > * Add support for Zve64x extension > * Relax vector register check in RISCV gdbstub > * Fix the element agnostic Vector function problem > * Fix Zvkb extension config > * Implement dynamic establishment of custom decoder > * Add th.sxstatus CSR emulation > * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions > * Check single width operator for vector fp widen instructions > * Check single width operator for vfncvt.rod.f.f.w > * Remove redudant SEW checking for vector fp narrow/widen instructions > * Prioritize pmp errors in raise_mmu_exception() > * Do not set mtval2 for non guest-page faults > * Remove experimental prefix from "B" extension > * Fixup CBO extension register calculation > * Fix the hart bit setting of AIA > * Fix reg_width in ricsv_gen_dynamic_vector_feature() > * Decode all of the pmpcfg and pmpaddr CSRs > > ---------------------------------------------------------------- Please have a look at this bugfix: https://lore.kernel.org/qemu-devel/20240419110514.69697-1-philmd@linaro.org/