[PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Clément Léger]

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fc2068ee4d..74318a925c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -670,11 +670,11 @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.43.0

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Daniel Henrique Barboza]

Palmer, Anup,

On 4/22/24 10:58, Clément Léger wrote:
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom uses change the semihosting exception number to 63
> which belongs to the range [48-63] in order to avoid any future
> collisions with reserved exception.


I didn't find any reference to a number for the SEMIHOST exception here:


https://github.com/riscv-non-isa/riscv-semihosting


Do we have any potential candidates? I would like to avoid, if possible, setting
RISCV_EXCP_SEMIHOST to 63 as a band-aid just to replace it later on by the real
value.


Thanks,

Daniel

> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> 
> ---
>   target/riscv/cpu_bits.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fc2068ee4d..74318a925c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -670,11 +670,11 @@ typedef enum RISCVException {
>       RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
>       RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
>       RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
> -    RISCV_EXCP_SEMIHOST = 0x10,
>       RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
>       RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
>       RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
>       RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
> +    RISCV_EXCP_SEMIHOST = 0x3f,
>   } RISCVException;
>   
>   #define RISCV_EXCP_INT_FLAG                0x80000000

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Richard Henderson]

On 4/22/24 10:45, Daniel Henrique Barboza wrote:
> Palmer, Anup,
> 
> On 4/22/24 10:58, Clément Léger wrote:
>> The current semihost exception number (16) is a reserved number (range
>> [16-17]). The upcoming double trap specification uses that number for
>> the double trap exception. Since the privileged spec (Table 22) defines
>> ranges for custom uses change the semihosting exception number to 63
>> which belongs to the range [48-63] in order to avoid any future
>> collisions with reserved exception.
> 
> 
> I didn't find any reference to a number for the SEMIHOST exception here:
> 
> 
> https://github.com/riscv-non-isa/riscv-semihosting
> 
> 
> Do we have any potential candidates? I would like to avoid, if possible, setting
> RISCV_EXCP_SEMIHOST to 63 as a band-aid just to replace it later on by the real
> value.

RISCV_EXCP_SEMIHOST is internal to the qemu implementation and will never be delivered to 
the guest.

I suggest using a number high in the >64 reserved range which will (likely) never be used 
by any implementation, including ones that *do* define implementation-specific exceptions. 
  Which seems more likely than not within the "implementation defined" range.

E.g. target/i386 uses 0x100+n for qemu internal exceptions.

But in any case, the number can be redefined at will and not cause compatibility issues.


r~

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Daniel Henrique Barboza]

On 4/22/24 16:44, Richard Henderson wrote:
> On 4/22/24 10:45, Daniel Henrique Barboza wrote:
>> Palmer, Anup,
>>
>> On 4/22/24 10:58, Clément Léger wrote:
>>> The current semihost exception number (16) is a reserved number (range
>>> [16-17]). The upcoming double trap specification uses that number for
>>> the double trap exception. Since the privileged spec (Table 22) defines
>>> ranges for custom uses change the semihosting exception number to 63
>>> which belongs to the range [48-63] in order to avoid any future
>>> collisions with reserved exception.
>>
>>
>> I didn't find any reference to a number for the SEMIHOST exception here:
>>
>>
>> https://github.com/riscv-non-isa/riscv-semihosting
>>
>>
>> Do we have any potential candidates? I would like to avoid, if possible, setting
>> RISCV_EXCP_SEMIHOST to 63 as a band-aid just to replace it later on by the real
>> value.
> 
> RISCV_EXCP_SEMIHOST is internal to the qemu implementation and will never be delivered to the guest.
> 
> I suggest using a number high in the >64 reserved range which will (likely) never be used by any implementation, including ones that *do* define implementation-specific exceptions.  Which seems more likely than not within the "implementation defined" range.
> 
> E.g. target/i386 uses 0x100+n for qemu internal exceptions.

I'm not sure if we have a range for risc-v qemu internal exceptions only. IIRC we don't.

If that's really the case I believe we could use whatever i386/ARM uses. At least we'll have some
standardization.


Thanks,

Daniel

> 
> But in any case, the number can be redefined at will and not cause compatibility issues.
> 
> 
> r~

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Clément Léger]

On 22/04/2024 21:58, Daniel Henrique Barboza wrote:
> 
> 
> On 4/22/24 16:44, Richard Henderson wrote:
>> On 4/22/24 10:45, Daniel Henrique Barboza wrote:
>>> Palmer, Anup,
>>>
>>> On 4/22/24 10:58, Clément Léger wrote:
>>>> The current semihost exception number (16) is a reserved number (range
>>>> [16-17]). The upcoming double trap specification uses that number for
>>>> the double trap exception. Since the privileged spec (Table 22) defines
>>>> ranges for custom uses change the semihosting exception number to 63
>>>> which belongs to the range [48-63] in order to avoid any future
>>>> collisions with reserved exception.
>>>
>>>
>>> I didn't find any reference to a number for the SEMIHOST exception here:
>>>
>>>
>>> https://github.com/riscv-non-isa/riscv-semihosting
>>>
>>>
>>> Do we have any potential candidates? I would like to avoid, if
>>> possible, setting
>>> RISCV_EXCP_SEMIHOST to 63 as a band-aid just to replace it later on
>>> by the real
>>> value.
>>
>> RISCV_EXCP_SEMIHOST is internal to the qemu implementation and will
>> never be delivered to the guest.
>>
>> I suggest using a number high in the >64 reserved range which will
>> (likely) never be used by any implementation, including ones that *do*
>> define implementation-specific exceptions.  Which seems more likely
>> than not within the "implementation defined" range.
>>
>> E.g. target/i386 uses 0x100+n for qemu internal exceptions.
> 
> I'm not sure if we have a range for risc-v qemu internal exceptions
> only. IIRC we don't.
> 
> If that's really the case I believe we could use whatever i386/ARM uses.
> At least we'll have some
> standardization.

The spec also states that numbers >= 64 are reserved which is why using
a one for custom use was making sense.

Thanks,

Clément

> 
> 
> Thanks,
> 
> Daniel
> 
>>
>> But in any case, the number can be redefined at will and not cause
>> compatibility issues.
>>
>>
>> r~

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Alistair Francis]

On Mon, Apr 22, 2024 at 11:59 PM Clément Léger <cleger@rivosinc.com> wrote:
>
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom uses change the semihosting exception number to 63
> which belongs to the range [48-63] in order to avoid any future
> collisions with reserved exception.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>  target/riscv/cpu_bits.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fc2068ee4d..74318a925c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -670,11 +670,11 @@ typedef enum RISCVException {
>      RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
>      RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
>      RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
> -    RISCV_EXCP_SEMIHOST = 0x10,
>      RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
>      RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
>      RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
>      RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
> +    RISCV_EXCP_SEMIHOST = 0x3f,
>  } RISCVException;
>
>  #define RISCV_EXCP_INT_FLAG                0x80000000
> --
> 2.43.0
>
>

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

[Alistair Francis]

On Mon, Apr 22, 2024 at 11:59 PM Clément Léger <cleger@rivosinc.com> wrote:
>
> The current semihost exception number (16) is a reserved number (range
> [16-17]). The upcoming double trap specification uses that number for
> the double trap exception. Since the privileged spec (Table 22) defines
> ranges for custom uses change the semihosting exception number to 63
> which belongs to the range [48-63] in order to avoid any future
> collisions with reserved exception.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> ---
>  target/riscv/cpu_bits.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fc2068ee4d..74318a925c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -670,11 +670,11 @@ typedef enum RISCVException {
>      RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
>      RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
>      RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
> -    RISCV_EXCP_SEMIHOST = 0x10,
>      RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
>      RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
>      RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
>      RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
> +    RISCV_EXCP_SEMIHOST = 0x3f,
>  } RISCVException;
>
>  #define RISCV_EXCP_INT_FLAG                0x80000000
> --
> 2.43.0
>
>