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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ee44bf470dsm2800803a12.0.2024.11.01.11.23.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Nov 2024 11:23:03 -0700 (PDT) Message-ID: <73bdeaf1-d000-4686-b76a-81c2bc7af123@linaro.org> Date: Fri, 1 Nov 2024 11:23:02 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley References: <20241101161125.1901394-1-peter.maydell@linaro.org> <20241101161125.1901394-3-peter.maydell@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241101161125.1901394-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/1/24 09:11, Peter Maydell wrote: > When calculating the index into the GIC's GPIO array for per-CPU > interrupts, we have to start with the number of SPIs. The code > currently hard-codes this to 'NUM_IRQS = 256'. However the number of > SPIs is set separately and implicitly by the value of > AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is > what we set the GIC num-irq property to). > > Define AST2700_MAX_IRQ as the total number of SPIs; this brings > AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the > number of SPIs not including the 32 internal interrupts. We can then > use AST2700_MAX_IRQ instead of the hardcoded 256. > > Signed-off-by: Peter Maydell > --- > hw/arm/aspeed_ast27x0.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c > index 5638a7a5781..7b246440952 100644 > --- a/hw/arm/aspeed_ast27x0.c > +++ b/hw/arm/aspeed_ast27x0.c > @@ -66,7 +66,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { > [ASPEED_DEV_GPIO] = 0x14C0B000, > }; > > -#define AST2700_MAX_IRQ 288 > +#define AST2700_MAX_IRQ 256 > > /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ > static const int aspeed_soc_ast2700_irqmap[] = { > @@ -403,7 +403,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > gicdev = DEVICE(&a->gic); > qdev_prop_set_uint32(gicdev, "revision", 3); > qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); > - qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); > + qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); > > redist_region_count = qlist_new(); > qlist_append_int(redist_region_count, sc->num_cpus); > @@ -417,8 +417,7 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) > > for (i = 0; i < sc->num_cpus; i++) { > DeviceState *cpudev = DEVICE(&a->cpu[i]); > - int NUM_IRQS = 256; > - int intidbase = NUM_IRQS + i * GIC_INTERNAL; > + int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; > > const int timer_irq[] = { > [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, Reviewed-by: Pierrick Bouvier