From: Marek Vasut <marex@denx.de>
To: "Bystricky, Juro" <juro.bystricky@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "crwulff@gmail.com" <crwulff@gmail.com>,
"jurobystricky@hotmail.com" <jurobystricky@hotmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v3 1/1] nios2: Add Altera JTAG UART emulation
Date: Thu, 9 Feb 2017 18:25:16 +0100 [thread overview]
Message-ID: <73cda6b5-245f-8753-f085-7defbd2fc167@denx.de> (raw)
In-Reply-To: <6E51916E4A1F32428260031F4C7CD2B6118FBD03@ORSMSX112.amr.corp.intel.com>
On 02/09/2017 05:34 PM, Bystricky, Juro wrote:
>> The code running on nios2 can issue unaligned access to the jtag uart
>> registers, yes ? If that happens, what happens on real HW and how is
>> this emulated ?
>
> Misaligned accesses to any registers would raise an exception.
> The exception is handled by interrupt controller, either "real"
> or emulated. Such access should never reach code for jtag uart.
>
> Also note we only allow access size 4 in the code:
>
> static const MemoryRegionOps juart_ops = {
> .read = altera_juart_read,
> .write = altera_juart_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> }
> };
This answers my question , thanks.
--
Best regards,
Marek Vasut
prev parent reply other threads:[~2017-02-09 17:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-08 23:06 [Qemu-devel] [PATCH v3 0/1] nios2: Add Altera JTAG UART emulation Juro Bystricky
2017-02-08 23:06 ` [Qemu-devel] [PATCH v3 1/1] " Juro Bystricky
2017-02-08 23:22 ` Marek Vasut
2017-02-08 23:33 ` Peter Maydell
2017-02-09 0:54 ` Bystricky, Juro
2017-02-09 8:46 ` Marek Vasut
2017-02-09 15:22 ` Bystricky, Juro
2017-02-09 15:37 ` Marek Vasut
2017-02-09 16:07 ` Bystricky, Juro
2017-02-09 16:13 ` Marek Vasut
2017-02-09 16:34 ` Bystricky, Juro
2017-02-09 17:25 ` Marek Vasut [this message]
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