From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
To: "bmeng@tinylab.org" <bmeng@tinylab.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "bin.meng@windriver.com" <bin.meng@windriver.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
Date: Thu, 1 Dec 2022 23:36:12 +0000 [thread overview]
Message-ID: <7460541cf49a4acd3f5881d9eade40a35c58e858.camel@wdc.com> (raw)
In-Reply-To: <20221201140811.142123-3-bmeng@tinylab.org>
On Thu, 2022-12-01 at 22:07 +0800, Bin Meng wrote:
> Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest
> build")
> the IBEX PLIC model was replaced with the SiFive PLIC model in the
> 'opentitan' machine but we forgot the add the dependency there.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> hw/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 167dc4cca6..1e4b58024f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -19,6 +19,7 @@ config MICROCHIP_PFSOC
> config OPENTITAN
> bool
> select IBEX
> + select SIFIVE_PLIC
> select UNIMP
>
> config SHAKTI_C
next prev parent reply other threads:[~2022-12-01 23:37 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 14:07 [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-01 14:07 ` [PATCH 02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:07 ` [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-01 23:36 ` Wilfred Mallawa [this message]
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-04 22:24 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 05/15] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-01 23:39 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-01 23:57 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 4:21 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-07 4:28 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-02 0:03 ` Wilfred Mallawa
2022-12-07 4:30 ` Alistair Francis
2022-12-07 8:29 ` Conor Dooley
2022-12-01 14:08 ` [PATCH 10/15] hw/riscv: sifive_e: " Bin Meng
2022-12-02 0:05 ` Wilfred Mallawa
2022-12-07 4:31 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-02 0:06 ` Wilfred Mallawa
2022-12-07 4:33 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 4:35 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-07 4:36 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-02 0:11 ` Wilfred Mallawa
2022-12-07 4:37 ` Alistair Francis
2022-12-07 10:11 ` Bin Meng
2022-12-01 14:08 ` [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-02 0:27 ` Wilfred Mallawa
2022-12-05 8:21 ` Bin Meng
2022-12-05 22:05 ` Wilfred Mallawa
2022-12-07 5:08 ` Alistair Francis
2022-12-04 22:21 ` [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
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