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Mon, 04 Nov 2024 02:24:35 -0800 (PST) Message-ID: <746d1fa4-aafd-415f-be67-94a7aee0b9de@linaro.org> Date: Mon, 4 Nov 2024 11:24:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculation To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley References: <20241101161125.1901394-1-peter.maydell@linaro.org> <20241101161125.1901394-3-peter.maydell@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20241101161125.1901394-3-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/11/24 13:11, Peter Maydell wrote: > When calculating the index into the GIC's GPIO array for per-CPU > interrupts, we have to start with the number of SPIs. The code > currently hard-codes this to 'NUM_IRQS = 256'. However the number of > SPIs is set separately and implicitly by the value of > AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is > what we set the GIC num-irq property to). > > Define AST2700_MAX_IRQ as the total number of SPIs; this brings > AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the > number of SPIs not including the 32 internal interrupts. We can then > use AST2700_MAX_IRQ instead of the hardcoded 256. > > Signed-off-by: Peter Maydell > --- > hw/arm/aspeed_ast27x0.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé