From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v4 20/20] target/riscv: Enable uxl field write
Date: Thu, 11 Nov 2021 19:23:52 +0100 [thread overview]
Message-ID: <74807b5d-debd-6140-aea7-d80b040a1d27@linaro.org> (raw)
In-Reply-To: <20211111155149.58172-21-zhiwei_liu@c-sky.com>
On 11/11/21 4:51 PM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 8 +++++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
Works for me.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-11-11 18:26 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-15 4:25 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-15 4:26 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-15 4:27 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-16 0:08 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-16 3:12 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-16 3:13 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-16 3:14 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-19 4:22 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-19 4:29 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-19 4:32 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-19 4:51 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-19 4:55 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-19 4:56 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-19 12:40 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-19 12:33 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-19 12:34 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-19 12:42 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-19 12:46 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 18:23 ` Richard Henderson [this message]
2021-11-19 12:55 ` Alistair Francis
2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis
2021-11-19 13:44 ` LIU Zhiwei
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