From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Mohamed Mediouni <mohamed@unpredictable.fr>,
qemu-devel@nongnu.org,
Richard Henderson <richard.henderson@linaro.org>
Cc: "Shannon Zhao" <shannon.zhaosl@gmail.com>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Mads Ynddal" <mads@ynddal.dk>,
"Cameron Esfahani" <dirty@apple.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
kvm@vger.kernel.org, "Igor Mammedov" <imammedo@redhat.com>,
qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
"Pedro Barbuda" <pbarbuda@microsoft.com>,
"Alexander Graf" <agraf@csgraf.de>,
"Sunil Muthuswamy" <sunilmut@microsoft.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Ani Sinha" <anisinha@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>
Subject: Re: [PATCH v6 11/23] whpx: add arm64 support
Date: Thu, 2 Oct 2025 07:13:52 +0200 [thread overview]
Message-ID: <749894d1-7301-419c-8a10-3ffbada016e3@linaro.org> (raw)
In-Reply-To: <20250920140124.63046-12-mohamed@unpredictable.fr>
Hi Mohamed,
On 20/9/25 16:01, Mohamed Mediouni wrote:
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
> accel/whpx/whpx-common.c | 1 +
> target/arm/meson.build | 1 +
> target/arm/whpx/meson.build | 3 +
> target/arm/whpx/whpx-all.c | 848 ++++++++++++++++++++++++++++++++++++
> 4 files changed, 853 insertions(+)
> create mode 100644 target/arm/whpx/meson.build
> create mode 100644 target/arm/whpx/whpx-all.c
> +struct whpx_reg_match {
> + WHV_REGISTER_NAME reg;
> + uint64_t offset;
> +};
> +
> +static const struct whpx_reg_match whpx_reg_match[] = {
> + { WHvArm64RegisterX0, offsetof(CPUARMState, xregs[0]) },
> + { WHvArm64RegisterX1, offsetof(CPUARMState, xregs[1]) },
> + { WHvArm64RegisterX2, offsetof(CPUARMState, xregs[2]) },
> + { WHvArm64RegisterX3, offsetof(CPUARMState, xregs[3]) },
> + { WHvArm64RegisterX4, offsetof(CPUARMState, xregs[4]) },
> + { WHvArm64RegisterX5, offsetof(CPUARMState, xregs[5]) },
> + { WHvArm64RegisterX6, offsetof(CPUARMState, xregs[6]) },
> + { WHvArm64RegisterX7, offsetof(CPUARMState, xregs[7]) },
> + { WHvArm64RegisterX8, offsetof(CPUARMState, xregs[8]) },
> + { WHvArm64RegisterX9, offsetof(CPUARMState, xregs[9]) },
> + { WHvArm64RegisterX10, offsetof(CPUARMState, xregs[10]) },
> + { WHvArm64RegisterX11, offsetof(CPUARMState, xregs[11]) },
> + { WHvArm64RegisterX12, offsetof(CPUARMState, xregs[12]) },
> + { WHvArm64RegisterX13, offsetof(CPUARMState, xregs[13]) },
> + { WHvArm64RegisterX14, offsetof(CPUARMState, xregs[14]) },
> + { WHvArm64RegisterX15, offsetof(CPUARMState, xregs[15]) },
> + { WHvArm64RegisterX16, offsetof(CPUARMState, xregs[16]) },
> + { WHvArm64RegisterX17, offsetof(CPUARMState, xregs[17]) },
> + { WHvArm64RegisterX18, offsetof(CPUARMState, xregs[18]) },
> + { WHvArm64RegisterX19, offsetof(CPUARMState, xregs[19]) },
> + { WHvArm64RegisterX20, offsetof(CPUARMState, xregs[20]) },
> + { WHvArm64RegisterX21, offsetof(CPUARMState, xregs[21]) },
> + { WHvArm64RegisterX22, offsetof(CPUARMState, xregs[22]) },
> + { WHvArm64RegisterX23, offsetof(CPUARMState, xregs[23]) },
> + { WHvArm64RegisterX24, offsetof(CPUARMState, xregs[24]) },
> + { WHvArm64RegisterX25, offsetof(CPUARMState, xregs[25]) },
> + { WHvArm64RegisterX26, offsetof(CPUARMState, xregs[26]) },
> + { WHvArm64RegisterX27, offsetof(CPUARMState, xregs[27]) },
> + { WHvArm64RegisterX28, offsetof(CPUARMState, xregs[28]) },
> + { WHvArm64RegisterFp, offsetof(CPUARMState, xregs[29]) },
> + { WHvArm64RegisterLr, offsetof(CPUARMState, xregs[30]) },
> + { WHvArm64RegisterPc, offsetof(CPUARMState, pc) },
> +};
> +
> +static const struct whpx_reg_match whpx_fpreg_match[] = {
> + { WHvArm64RegisterQ0, offsetof(CPUARMState, vfp.zregs[0]) },
> + { WHvArm64RegisterQ1, offsetof(CPUARMState, vfp.zregs[1]) },
> + { WHvArm64RegisterQ2, offsetof(CPUARMState, vfp.zregs[2]) },
> + { WHvArm64RegisterQ3, offsetof(CPUARMState, vfp.zregs[3]) },
> + { WHvArm64RegisterQ4, offsetof(CPUARMState, vfp.zregs[4]) },
> + { WHvArm64RegisterQ5, offsetof(CPUARMState, vfp.zregs[5]) },
> + { WHvArm64RegisterQ6, offsetof(CPUARMState, vfp.zregs[6]) },
> + { WHvArm64RegisterQ7, offsetof(CPUARMState, vfp.zregs[7]) },
> + { WHvArm64RegisterQ8, offsetof(CPUARMState, vfp.zregs[8]) },
> + { WHvArm64RegisterQ9, offsetof(CPUARMState, vfp.zregs[9]) },
> + { WHvArm64RegisterQ10, offsetof(CPUARMState, vfp.zregs[10]) },
> + { WHvArm64RegisterQ11, offsetof(CPUARMState, vfp.zregs[11]) },
> + { WHvArm64RegisterQ12, offsetof(CPUARMState, vfp.zregs[12]) },
> + { WHvArm64RegisterQ13, offsetof(CPUARMState, vfp.zregs[13]) },
> + { WHvArm64RegisterQ14, offsetof(CPUARMState, vfp.zregs[14]) },
> + { WHvArm64RegisterQ15, offsetof(CPUARMState, vfp.zregs[15]) },
> + { WHvArm64RegisterQ16, offsetof(CPUARMState, vfp.zregs[16]) },
> + { WHvArm64RegisterQ17, offsetof(CPUARMState, vfp.zregs[17]) },
> + { WHvArm64RegisterQ18, offsetof(CPUARMState, vfp.zregs[18]) },
> + { WHvArm64RegisterQ19, offsetof(CPUARMState, vfp.zregs[19]) },
> + { WHvArm64RegisterQ20, offsetof(CPUARMState, vfp.zregs[20]) },
> + { WHvArm64RegisterQ21, offsetof(CPUARMState, vfp.zregs[21]) },
> + { WHvArm64RegisterQ22, offsetof(CPUARMState, vfp.zregs[22]) },
> + { WHvArm64RegisterQ23, offsetof(CPUARMState, vfp.zregs[23]) },
> + { WHvArm64RegisterQ24, offsetof(CPUARMState, vfp.zregs[24]) },
> + { WHvArm64RegisterQ25, offsetof(CPUARMState, vfp.zregs[25]) },
> + { WHvArm64RegisterQ26, offsetof(CPUARMState, vfp.zregs[26]) },
> + { WHvArm64RegisterQ27, offsetof(CPUARMState, vfp.zregs[27]) },
> + { WHvArm64RegisterQ28, offsetof(CPUARMState, vfp.zregs[28]) },
> + { WHvArm64RegisterQ29, offsetof(CPUARMState, vfp.zregs[29]) },
> + { WHvArm64RegisterQ30, offsetof(CPUARMState, vfp.zregs[30]) },
> + { WHvArm64RegisterQ31, offsetof(CPUARMState, vfp.zregs[31]) },
> +};
> +
> +#define WHPX_SYSREG(crn, crm, op0, op1, op2) \
> + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
> +
> +struct whpx_sreg_match {
> + WHV_REGISTER_NAME reg;
> + uint32_t key;
> + bool global;
> + uint32_t cp_idx;
> +};
> +
> +static struct whpx_sreg_match whpx_sreg_match[] = {
> + { WHvArm64RegisterDbgbvr0El1, WHPX_SYSREG(0, 0, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr0El1, WHPX_SYSREG(0, 0, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr0El1, WHPX_SYSREG(0, 0, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr0El1, WHPX_SYSREG(0, 0, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr0El1, WHPX_SYSREG(0, 1, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr0El1, WHPX_SYSREG(0, 1, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr0El1, WHPX_SYSREG(0, 1, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr0El1, WHPX_SYSREG(0, 1, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr2El1, WHPX_SYSREG(0, 2, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr2El1, WHPX_SYSREG(0, 2, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr2El1, WHPX_SYSREG(0, 2, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr2El1, WHPX_SYSREG(0, 2, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr3El1, WHPX_SYSREG(0, 3, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr3El1, WHPX_SYSREG(0, 3, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr3El1, WHPX_SYSREG(0, 3, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr3El1, WHPX_SYSREG(0, 3, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr4El1, WHPX_SYSREG(0, 4, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr4El1, WHPX_SYSREG(0, 4, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr4El1, WHPX_SYSREG(0, 4, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr4El1, WHPX_SYSREG(0, 4, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr5El1, WHPX_SYSREG(0, 5, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr5El1, WHPX_SYSREG(0, 5, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr5El1, WHPX_SYSREG(0, 5, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr5El1, WHPX_SYSREG(0, 5, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr6El1, WHPX_SYSREG(0, 6, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr6El1, WHPX_SYSREG(0, 6, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr6El1, WHPX_SYSREG(0, 6, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr6El1, WHPX_SYSREG(0, 6, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr7El1, WHPX_SYSREG(0, 7, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr7El1, WHPX_SYSREG(0, 7, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr7El1, WHPX_SYSREG(0, 7, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr7El1, WHPX_SYSREG(0, 7, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr8El1, WHPX_SYSREG(0, 8, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr8El1, WHPX_SYSREG(0, 8, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr8El1, WHPX_SYSREG(0, 8, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr8El1, WHPX_SYSREG(0, 8, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr9El1, WHPX_SYSREG(0, 9, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr9El1, WHPX_SYSREG(0, 9, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr9El1, WHPX_SYSREG(0, 9, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr9El1, WHPX_SYSREG(0, 9, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr10El1, WHPX_SYSREG(0, 10, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr10El1, WHPX_SYSREG(0, 10, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr10El1, WHPX_SYSREG(0, 10, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr10El1, WHPX_SYSREG(0, 10, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr11El1, WHPX_SYSREG(0, 11, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr11El1, WHPX_SYSREG(0, 11, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr11El1, WHPX_SYSREG(0, 11, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr11El1, WHPX_SYSREG(0, 11, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr12El1, WHPX_SYSREG(0, 12, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr12El1, WHPX_SYSREG(0, 12, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr12El1, WHPX_SYSREG(0, 12, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr12El1, WHPX_SYSREG(0, 12, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr13El1, WHPX_SYSREG(0, 13, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr13El1, WHPX_SYSREG(0, 13, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr13El1, WHPX_SYSREG(0, 13, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr13El1, WHPX_SYSREG(0, 13, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr14El1, WHPX_SYSREG(0, 14, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr14El1, WHPX_SYSREG(0, 14, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr14El1, WHPX_SYSREG(0, 14, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr14El1, WHPX_SYSREG(0, 14, 2, 0, 7) },
> +
> + { WHvArm64RegisterDbgbvr15El1, WHPX_SYSREG(0, 15, 2, 0, 4) },
> + { WHvArm64RegisterDbgbcr15El1, WHPX_SYSREG(0, 15, 2, 0, 5) },
> + { WHvArm64RegisterDbgwvr15El1, WHPX_SYSREG(0, 15, 2, 0, 6) },
> + { WHvArm64RegisterDbgwcr15El1, WHPX_SYSREG(0, 15, 2, 0, 7) },
> +#ifdef SYNC_NO_RAW_REGS
> + /*
> + * The registers below are manually synced on init because they are
> + * marked as NO_RAW. We still list them to make number space sync easier.
> + */
> + { WHvArm64RegisterMidrEl1, WHPX_SYSREG(0, 0, 3, 0, 0) },
> + { WHvArm64RegisterMpidrEl1, WHPX_SYSREG(0, 0, 3, 0, 5) },
> + { WHvArm64RegisterIdPfr0El1, WHPX_SYSREG(0, 4, 3, 0, 0) },
> +#endif
> + { WHvArm64RegisterIdAa64Pfr1El1, WHPX_SYSREG(0, 4, 3, 0, 1), true },
> + { WHvArm64RegisterIdAa64Dfr0El1, WHPX_SYSREG(0, 5, 3, 0, 0), true },
> + { WHvArm64RegisterIdAa64Dfr1El1, WHPX_SYSREG(0, 5, 3, 0, 1), true },
> + { WHvArm64RegisterIdAa64Isar0El1, WHPX_SYSREG(0, 6, 3, 0, 0), true },
> + { WHvArm64RegisterIdAa64Isar1El1, WHPX_SYSREG(0, 6, 3, 0, 1), true },
> +#ifdef SYNC_NO_MMFR0
> + /* We keep the hardware MMFR0 around. HW limits are there anyway */
> + { WHvArm64RegisterIdAa64Mmfr0El1, WHPX_SYSREG(0, 7, 3, 0, 0) },
> +#endif
> + { WHvArm64RegisterIdAa64Mmfr1El1, WHPX_SYSREG(0, 7, 3, 0, 1), true },
> + { WHvArm64RegisterIdAa64Mmfr2El1, WHPX_SYSREG(0, 7, 3, 0, 2), true },
> + { WHvArm64RegisterIdAa64Mmfr3El1, WHPX_SYSREG(0, 7, 3, 0, 3), true },
> +
> + { WHvArm64RegisterMdscrEl1, WHPX_SYSREG(0, 2, 2, 0, 2) },
> + { WHvArm64RegisterSctlrEl1, WHPX_SYSREG(1, 0, 3, 0, 0) },
> + { WHvArm64RegisterCpacrEl1, WHPX_SYSREG(1, 0, 3, 0, 2) },
> + { WHvArm64RegisterTtbr0El1, WHPX_SYSREG(2, 0, 3, 0, 0) },
> + { WHvArm64RegisterTtbr1El1, WHPX_SYSREG(2, 0, 3, 0, 1) },
> + { WHvArm64RegisterTcrEl1, WHPX_SYSREG(2, 0, 3, 0, 2) },
> +
> + { WHvArm64RegisterApiAKeyLoEl1, WHPX_SYSREG(2, 1, 3, 0, 0) },
> + { WHvArm64RegisterApiAKeyHiEl1, WHPX_SYSREG(2, 1, 3, 0, 1) },
> + { WHvArm64RegisterApiBKeyLoEl1, WHPX_SYSREG(2, 1, 3, 0, 2) },
> + { WHvArm64RegisterApiBKeyHiEl1, WHPX_SYSREG(2, 1, 3, 0, 3) },
> + { WHvArm64RegisterApdAKeyLoEl1, WHPX_SYSREG(2, 2, 3, 0, 0) },
> + { WHvArm64RegisterApdAKeyHiEl1, WHPX_SYSREG(2, 2, 3, 0, 1) },
> + { WHvArm64RegisterApdBKeyLoEl1, WHPX_SYSREG(2, 2, 3, 0, 2) },
> + { WHvArm64RegisterApdBKeyHiEl1, WHPX_SYSREG(2, 2, 3, 0, 3) },
> + { WHvArm64RegisterApgAKeyLoEl1, WHPX_SYSREG(2, 3, 3, 0, 0) },
> + { WHvArm64RegisterApgAKeyHiEl1, WHPX_SYSREG(2, 3, 3, 0, 1) },
> +
> + { WHvArm64RegisterSpsrEl1, WHPX_SYSREG(4, 0, 3, 0, 0) },
> + { WHvArm64RegisterElrEl1, WHPX_SYSREG(4, 0, 3, 0, 1) },
> + { WHvArm64RegisterSpEl1, WHPX_SYSREG(4, 1, 3, 0, 0) },
> + { WHvArm64RegisterEsrEl1, WHPX_SYSREG(5, 2, 3, 0, 0) },
> + { WHvArm64RegisterFarEl1, WHPX_SYSREG(6, 0, 3, 0, 0) },
> + { WHvArm64RegisterParEl1, WHPX_SYSREG(7, 4, 3, 0, 0) },
> + { WHvArm64RegisterMairEl1, WHPX_SYSREG(10, 2, 3, 0, 0) },
> + { WHvArm64RegisterVbarEl1, WHPX_SYSREG(12, 0, 3, 0, 0) },
> + { WHvArm64RegisterContextidrEl1, WHPX_SYSREG(13, 0, 3, 0, 1) },
> + { WHvArm64RegisterTpidrEl1, WHPX_SYSREG(13, 0, 3, 0, 4) },
> + { WHvArm64RegisterCntkctlEl1, WHPX_SYSREG(14, 1, 3, 0, 0) },
> + { WHvArm64RegisterCsselrEl1, WHPX_SYSREG(0, 0, 3, 2, 0) },
> + { WHvArm64RegisterTpidrEl0, WHPX_SYSREG(13, 0, 3, 3, 2) },
> + { WHvArm64RegisterTpidrroEl0, WHPX_SYSREG(13, 0, 3, 3, 3) },
> + { WHvArm64RegisterCntvCtlEl0, WHPX_SYSREG(14, 3, 3, 3, 1) },
> + { WHvArm64RegisterCntvCvalEl0, WHPX_SYSREG(14, 3, 3, 3, 2) },
> + { WHvArm64RegisterSpEl1, WHPX_SYSREG(4, 1, 3, 4, 0) },
> +};
To ease maintenance, this array should follow this equivalent
changeset:
$ git log --oneline a648af4885b~..bffe756ea10
bffe756ea10 target/arm/hvf: Sort the cpreg_indexes array
98c2af435e6 target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_list
e6728fb3492 target/arm/hvf: Remove hvf_sreg_match.key
7d4d89a4377 target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMID
8da60618b6d target/arm/hvf: Reorder DEF_SYSREG arguments
a648af4885b target/arm/hvf: Split out sysreg.c.inc
next prev parent reply other threads:[~2025-10-02 5:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-20 14:01 [PATCH v6 00/23] WHPX support for Arm Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 01/23] target/arm/kvm: add constants for new PSCI versions Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 02/23] accel/system: Introduce hwaccel_enabled() helper Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 03/23] hw/arm: virt: add GICv2m for the case when ITS is not available Mohamed Mediouni
2025-09-25 16:24 ` Peter Maydell
2025-10-02 4:30 ` Mohamed Mediouni
2025-10-27 16:03 ` Peter Maydell
2025-10-27 16:53 ` Mohamed Mediouni
2025-10-27 17:07 ` Peter Maydell
2025-09-20 14:01 ` [PATCH v6 04/23] tests: data: update AArch64 ACPI tables Mohamed Mediouni
2025-09-25 15:59 ` Peter Maydell
2025-09-20 14:01 ` [PATCH v6 05/23] whpx: Move around files before introducing AArch64 support Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 06/23] whpx: reshuffle common code Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 07/23] whpx: ifdef out winhvemulation on non-x86_64 Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 08/23] whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 09/23] hw, target, accel: whpx: change apic_in_platform to kernel_irqchip Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 10/23] whpx: interrupt controller support Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 11/23] whpx: add arm64 support Mohamed Mediouni
2025-10-02 5:13 ` Philippe Mathieu-Daudé [this message]
2025-09-20 14:01 ` [PATCH v6 12/23] whpx: copy over memory management logic from hvf Mohamed Mediouni
2025-10-02 5:16 ` Philippe Mathieu-Daudé
2025-09-20 14:01 ` [PATCH v6 13/23] target/arm: cpu: mark WHPX as supporting PSCI 1.3 Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 14/23] hw/arm: virt: cleanly fail on attempt to use the platform vGIC together with ITS Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 15/23] whpx: arm64: clamp down IPA size Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 16/23] hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 17/23] whpx: arm64: implement -cpu host Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 18/23] target/arm: whpx: instantiate GIC early Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 19/23] whpx: arm64: gicv3: add migration blocker Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 20/23] whpx: enable arm64 builds Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 21/23] MAINTAINERS: update maintainers for WHPX Mohamed Mediouni
2025-09-20 14:01 ` [PATCH v6 22/23] docs: arm: update virt machine model description Mohamed Mediouni
2025-09-25 16:02 ` Peter Maydell
2025-09-20 14:01 ` [PATCH v6 23/23] whpx: apic: use non-deprecated APIs to control interrupt controller state Mohamed Mediouni
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