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From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <alex.williamson@redhat.com>, <clg@redhat.com>,
	<eric.auger@redhat.com>, <mst@redhat.com>, <peterx@redhat.com>,
	<jasowang@redhat.com>, <jgg@nvidia.com>, <nicolinc@nvidia.com>,
	<joao.m.martins@oracle.com>, <clement.mathieu--drif@eviden.com>,
	<kevin.tian@intel.com>, <chao.p.peng@intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode
Date: Mon, 4 Nov 2024 11:16:20 +0800	[thread overview]
Message-ID: <74b6f85d-f5b5-48da-8bc5-bfe721250687@intel.com> (raw)
In-Reply-To: <20240930092631.2997543-15-zhenzhong.duan@intel.com>

On 2024/9/30 17:26, Zhenzhong Duan wrote:
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
> 
> However, 5-level paging translation emulation is unsupported yet.
> That means the only supported value for aw_bits is 48.
> 
> So default aw_bits to 48 in scalable modern mode. In other cases,
> it is still default to 39 for backward compatibility.
> 
> Add a check to ensure user specified value is 48 in modern mode
> for now.

this is not a simple check. I think your patch makes an auto selection
of aw_bits.

> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
> ---
>   include/hw/i386/intel_iommu.h |  2 +-
>   hw/i386/intel_iommu.c         | 10 +++++++++-
>   2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index b843d069cc..48134bda11 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -45,7 +45,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
>   #define DMAR_REG_SIZE               0x230
>   #define VTD_HOST_AW_39BIT           39
>   #define VTD_HOST_AW_48BIT           48
> -#define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
> +#define VTD_HOST_AW_AUTO            0xff
>   #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
>   
>   #define DMAR_REPORT_F_INTR          (1)
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 91d7b1abfa..068a08f522 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3776,7 +3776,7 @@ static Property vtd_properties[] = {
>                               ON_OFF_AUTO_AUTO),
>       DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
>       DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
> -                      VTD_HOST_ADDRESS_WIDTH),
> +                      VTD_HOST_AW_AUTO),
>       DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
>       DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
>       DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
> @@ -4683,6 +4683,14 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
>           }
>       }
>   
> +    if (s->aw_bits == VTD_HOST_AW_AUTO) {
> +        if (s->scalable_modern) {
> +            s->aw_bits = VTD_HOST_AW_48BIT;
> +        } else {
> +            s->aw_bits = VTD_HOST_AW_39BIT;
> +        }
> +    }

If the default value of s->aw_bits is still 39, you don't know if it's
set by the admin or the orchestration stack. This is why you need
to change it. right?

> +
>       if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT &&
>           s->aw_bits != VTD_HOST_AW_48BIT) {
>           error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d",

-- 
Regards,
Yi Liu


  reply	other threads:[~2024-11-04  3:12 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-30  9:26 [PATCH v4 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-09-30  9:26 ` [PATCH v4 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-09-30  9:26 ` [PATCH v4 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-09-30  9:26 ` [PATCH v4 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-10-04  5:22   ` CLEMENT MATHIEU--DRIF
2024-11-03 14:21   ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-04  2:49   ` Yi Liu
2024-11-04  7:37     ` CLEMENT MATHIEU--DRIF
2024-11-04  8:45       ` Yi Liu
2024-11-04 11:46         ` Duan, Zhenzhong
2024-11-04 11:50           ` Michael S. Tsirkin
2024-11-04 11:55             ` Duan, Zhenzhong
2024-11-04 12:01               ` Michael S. Tsirkin
2024-11-04 12:03                 ` Duan, Zhenzhong
2024-09-30  9:26 ` [PATCH v4 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-09-30  9:26 ` [PATCH v4 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-03 14:21   ` Yi Liu
2024-11-04  3:05     ` Duan, Zhenzhong
2024-11-04  7:02       ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-03 14:22   ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-11-04  2:49   ` Yi Liu
2024-11-08  3:15   ` Jason Wang
2024-09-30  9:26 ` [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-04  2:50   ` Yi Liu
2024-11-04  3:38     ` Duan, Zhenzhong
2024-11-04  7:36       ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-04  2:50   ` Yi Liu
2024-11-04  5:40     ` Duan, Zhenzhong
2024-11-04  7:05       ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-04  2:50   ` Yi Liu
2024-11-04  5:47     ` Duan, Zhenzhong
2024-09-30  9:26 ` [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-11-04  2:51   ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-04  3:05   ` Yi Liu
2024-11-04  8:15     ` Duan, Zhenzhong
2024-11-05  6:29       ` Yi Liu
2024-11-05  7:25         ` Duan, Zhenzhong
2024-11-08  4:39   ` Jason Wang
2024-09-30  9:26 ` [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode Zhenzhong Duan
2024-11-04  3:16   ` Yi Liu [this message]
2024-11-04  3:19     ` Duan, Zhenzhong
2024-11-04  7:25       ` Yi Liu
2024-11-08  4:41   ` Jason Wang
2024-11-08  5:30     ` Duan, Zhenzhong
2024-11-11  1:24       ` Jason Wang
2024-11-11  2:58         ` Duan, Zhenzhong
2024-11-11  3:03           ` Jason Wang
2024-09-30  9:26 ` [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for " Zhenzhong Duan
2024-11-04  4:25   ` Yi Liu
2024-11-04  6:25     ` Duan, Zhenzhong
2024-11-04  7:23       ` Yi Liu
2024-11-05  3:11         ` Duan, Zhenzhong
2024-11-05  5:56           ` Yi Liu
2024-11-05  6:03             ` Duan, Zhenzhong
2024-11-05  6:26               ` Yi Liu
2024-09-30  9:26 ` [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-04  7:00   ` Yi Liu
2024-11-08  4:45     ` Jason Wang
2024-09-30  9:26 ` [PATCH v4 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-09-30  9:52   ` Duan, Zhenzhong
2024-10-25  6:32 ` [PATCH v4 00/17] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong

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