From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs
Date: Thu, 2 Feb 2023 11:52:16 +0100 [thread overview]
Message-ID: <74cbaf9c-34f1-3aaa-0759-51982d057473@linaro.org> (raw)
In-Reply-To: <7592c27c-0c98-d52c-fecc-ac2b261ecbb3@linaro.org>
On 2/2/23 11:47, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 3/7/20 17:53, Peter Maydell wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> At the moment the virtio-iommu translates MSI transactions.
>> This behavior is inherited from ARM SMMU. The virt machine
>> code knows where the guest MSI doorbells are so we can easily
>> declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
>> setting the guest will not map MSIs through the IOMMU and those
>> transactions will be simply bypassed.
>>
>> Depending on which MSI controller is in use (ITS or GICV2M),
>> we declare either:
>> - the ITS interrupt translation space (ITS_base + 0x10000),
>> containing the GITS_TRANSLATOR or
>> - The GICV2M single frame, containing the MSI_SETSP_NS register.
>>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Message-id: 20200629070404.10969-6-eric.auger@redhat.com
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> include/hw/arm/virt.h | 7 +++++++
>> hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++
>> 2 files changed, 37 insertions(+)
>
>
>> static void create_gic(VirtMachineState *vms)
>> @@ -2198,8 +2200,36 @@ out:
>> static void virt_machine_device_pre_plug_cb(HotplugHandler
>> *hotplug_dev,
>> DeviceState *dev, Error
>> **errp)
>> {
>> + VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
>> +
>> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
>> virt_memory_pre_plug(hotplug_dev, dev, errp);
>> + } else if (object_dynamic_cast(OBJECT(dev),
>> TYPE_VIRTIO_IOMMU_PCI)) {
>> + hwaddr db_start = 0, db_end = 0;
>> + char *resv_prop_str;
>> +
>> + switch (vms->msi_controller) {
>> + case VIRT_MSI_CTRL_NONE:
>> + return;
>> + case VIRT_MSI_CTRL_ITS:
>> + /* GITS_TRANSLATER page */
>> + db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
>> + db_end = base_memmap[VIRT_GIC_ITS].base +
>> + base_memmap[VIRT_GIC_ITS].size - 1;
>> + break;
>> + case VIRT_MSI_CTRL_GICV2M:
>> + /* MSI_SETSPI_NS page */
>> + db_start = base_memmap[VIRT_GIC_V2M].base;
>> + db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
>> + break;
>> + }
>> + resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
>> + db_start, db_end,
>> + VIRTIO_IOMMU_RESV_MEM_T_MSI);
>> +
>> + qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
>
> Where is "len-reserved-regions" declared?
>
> Since qdev_prop_set_uint32() uses &error_abort, isn't this call
> aborting the process? I am confused how this code path is exercised,
> what am I missing?
The call path is:
qdev_prop_set_uint32 ->
object_property_set_int ->
object_property_set_qobject ->
object_property_set ->
object_property_find_err
So QEMU should abort displaying:
"Property 'virtio-iommu-pci.len-reserved-regions' not found".
>> + qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
>> + g_free(resv_prop_str);
>> }
>> }
next prev parent reply other threads:[~2023-02-02 10:52 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 16:53 [PULL 00/34] target-arm queue Peter Maydell
2020-07-03 16:53 ` [PULL 01/34] Add a phy-num property to the i.MX FEC emulator Peter Maydell
2020-07-03 16:53 ` [PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface Peter Maydell
2020-07-03 16:53 ` [PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board Peter Maydell
2020-07-03 16:53 ` [PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION Peter Maydell
2020-07-03 16:53 ` [PULL 05/34] virtio-iommu: Implement RESV_MEM probe request Peter Maydell
2020-07-05 18:21 ` Peter Maydell
2020-07-08 14:40 ` Auger Eric
2020-07-03 16:53 ` [PULL 06/34] virtio-iommu: Handle reserved regions in the translation process Peter Maydell
2020-07-03 16:53 ` [PULL 07/34] virtio-iommu-pci: Add array of Interval properties Peter Maydell
2020-07-03 16:53 ` [PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs Peter Maydell
2023-02-02 10:47 ` Philippe Mathieu-Daudé
2023-02-02 10:52 ` Philippe Mathieu-Daudé [this message]
2023-02-02 10:58 ` Peter Maydell
2023-02-02 11:07 ` Philippe Mathieu-Daudé
2023-02-02 13:06 ` Eric Auger
2020-07-03 16:53 ` [PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS Peter Maydell
2020-07-03 16:53 ` [PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection Peter Maydell
2020-07-03 16:53 ` [PULL 11/34] tests/acpi: remove stale allowed tables Peter Maydell
2020-07-03 16:53 ` [PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes Peter Maydell
2020-07-03 16:53 ` [PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types Peter Maydell
2020-07-03 16:53 ` [PULL 14/34] tests/acpi: virt: update golden masters for DSDT Peter Maydell
2020-07-03 16:53 ` [PULL 15/34] target/arm: Fix temp double-free in sve ldr/str Peter Maydell
2020-07-03 16:53 ` [PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct Peter Maydell
2020-07-03 16:53 ` [PULL 17/34] hw/arm/spitz: Detabify Peter Maydell
2020-07-03 16:53 ` [PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class Peter Maydell
2020-07-03 16:53 ` [PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState Peter Maydell
2020-07-03 16:53 ` [PULL 20/34] hw/arm/spitz: Keep pointers to scp0, scp1 " Peter Maydell
2020-07-03 16:53 ` [PULL 21/34] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals Peter Maydell
2020-07-03 16:53 ` [PULL 22/34] hw/misc/max111x: provide QOM properties for setting initial values Peter Maydell
2020-07-03 16:53 ` [PULL 23/34] hw/misc/max111x: Don't use vmstate_register() Peter Maydell
2020-07-03 16:53 ` [PULL 24/34] ssi: Add ssi_realize_and_unref() Peter Maydell
2020-07-03 16:53 ` [PULL 25/34] hw/arm/spitz: Use max111x properties to set initial values Peter Maydell
2020-07-03 16:53 ` [PULL 26/34] hw/misc/max111x: Use GPIO lines rather than max111x_set_input() Peter Maydell
2020-07-03 16:53 ` [PULL 27/34] hw/misc/max111x: Create header file for documentation, TYPE_ macros Peter Maydell
2020-07-03 16:53 ` [PULL 28/34] hw/arm/spitz: Encapsulate misc GPIO handling in a device Peter Maydell
2020-07-03 16:54 ` [PULL 29/34] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses Peter Maydell
2020-07-03 16:54 ` [PULL 30/34] hw/arm/spitz: " Peter Maydell
2020-07-03 16:54 ` [PULL 31/34] hw/arm/pxa2xx_pic: " Peter Maydell
2020-07-03 16:54 ` [PULL 32/34] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg Peter Maydell
2020-07-03 16:54 ` [PULL 33/34] Replace uses of FROM_SSI_SLAVE() macro with QOM casts Peter Maydell
2020-07-03 16:54 ` [PULL 34/34] Deprecate TileGX port Peter Maydell
2020-07-03 17:50 ` [PULL 00/34] target-arm queue no-reply
2020-07-04 17:43 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=74cbaf9c-34f1-3aaa-0759-51982d057473@linaro.org \
--to=philmd@linaro.org \
--cc=eric.auger@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).