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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id 15-20020a62190f000000b0058dc1d54db1sm4378899pfz.206.2023.01.25.20.11.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Jan 2023 20:11:49 -0800 (PST) Message-ID: <74fe37d9-331c-7e00-e642-365f1a04ff80@linaro.org> Date: Wed, 25 Jan 2023 18:11:45 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza , qemu-devel@nongnu.org References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-7-richard.henderson@linaro.org> <877cxaqpxi.fsf@linaro.org> From: Richard Henderson In-Reply-To: <877cxaqpxi.fsf@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/25/23 11:09, Alex Bennée wrote: >> -static const int tcg_target_call_oarg_regs[2] = { >> - TCG_REG_R0, TCG_REG_R1 >> -}; >> + >> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) >> +{ >> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); >> + tcg_debug_assert(slot >= 0 && slot <= 3); >> + return TCG_REG_R0 + slot; >> +} > > So this is now returning allocations of TCG_REG_R0 to TCG_REG_R3? Yes, should have mentioned in the patch description. Done. > Do we > have to take care to get things right if slot is ever bigger w.r.t. > tcg_target_reg_alloc_order? No, reg_alloc_order is optimization for call-saved vs call-clobbered vs call arguments. It should not affect correctness at all. Nor will it ever affect call return -- those registers die immediately before the call, and become live with these values immediately after the call. r~