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[95.127.154.92]) by smtp.gmail.com with ESMTPSA id t185sm596879wmf.45.2019.11.21.10.55.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Nov 2019 10:55:36 -0800 (PST) Subject: Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic To: Michael Rolnik , richard.henderson@linaro.org References: <20191029212430.20617-1-mrolnik@gmail.com> <20191029212430.20617-2-mrolnik@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <750745b9-e51c-3757-3eb6-ffce51042d9c@redhat.com> Date: Thu, 21 Nov 2019 19:55:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191029212430.20617-2-mrolnik@gmail.com> Content-Language: en-US X-MC-Unique: _6BpcM3rPFuUTkK26Y3heQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , Joaquin de Andres , thuth@redhat.com, qemu-devel@nongnu.org, dovgaluk@ispras.ru, imammedo@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Michael, On 10/29/19 10:24 PM, Michael Rolnik wrote: > This includes: > - CPU data structures > - object model classes and functions > - migration functions > - GDB hooks >=20 > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah Harris > Signed-off-by: Michael Rolnik > Acked-by: Igor Mammedov > --- > gdb-xml/avr-cpu.xml | 49 ++++ > target/avr/cpu-param.h | 37 +++ > target/avr/cpu-qom.h | 54 ++++ > target/avr/cpu.c | 576 +++++++++++++++++++++++++++++++++++++++++ > target/avr/cpu.h | 253 ++++++++++++++++++ > target/avr/gdbstub.c | 85 ++++++ > target/avr/machine.c | 121 +++++++++ > 7 files changed, 1175 insertions(+) > create mode 100644 gdb-xml/avr-cpu.xml > create mode 100644 target/avr/cpu-param.h > create mode 100644 target/avr/cpu-qom.h > create mode 100644 target/avr/cpu.c > create mode 100644 target/avr/cpu.h > create mode 100644 target/avr/gdbstub.c > create mode 100644 target/avr/machine.c >=20 > diff --git a/gdb-xml/avr-cpu.xml b/gdb-xml/avr-cpu.xml > new file mode 100644 > index 0000000000..c4747f5b40 > --- /dev/null > +++ b/gdb-xml/avr-cpu.xml > @@ -0,0 +1,49 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h > new file mode 100644 > index 0000000000..ccd1ea3429 > --- /dev/null > +++ b/target/avr/cpu-param.h > @@ -0,0 +1,37 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef AVR_CPU_PARAM_H > +#define AVR_CPU_PARAM_H 1 > + > +#define TARGET_LONG_BITS 32 > +/* > + * TARGET_PAGE_BITS cannot be more than 8 bits because > + * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and the= y > + * should be implemented as a device and not memory > + * 2. SRAM starts at the address 0x0100 > + */ > +#define TARGET_PAGE_BITS 8 > +#define TARGET_PHYS_ADDR_SPACE_BITS 24 > +#define TARGET_VIRT_ADDR_SPACE_BITS 24 > +#define NB_MMU_MODES 2 > + > + > +#endif > diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h > new file mode 100644 > index 0000000000..e28b58c897 > --- /dev/null > +++ b/target/avr/cpu-qom.h > @@ -0,0 +1,54 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef QEMU_AVR_QOM_H > +#define QEMU_AVR_QOM_H > + > +#include "hw/core/cpu.h" > + > +#define TYPE_AVR_CPU "avr-cpu" > + > +#define AVR_CPU_CLASS(klass) \ > + OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU) > +#define AVR_CPU(obj) \ > + OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU) > +#define AVR_CPU_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU) > + > +/** > + * AVRCPUClass: > + * @parent_realize: The parent class' realize handler. > + * @parent_reset: The parent class' reset handler. > + * @vr: Version Register value. > + * > + * A AVR CPU model. > + */ > +typedef struct AVRCPUClass { > + /*< private >*/ > + CPUClass parent_class; > + /*< public >*/ > + DeviceRealize parent_realize; > + void (*parent_reset)(CPUState *cpu); > +} AVRCPUClass; > + > +typedef struct AVRCPU AVRCPU; > + > + > +#endif /* !defined (QEMU_AVR_CPU_QOM_H) */ > diff --git a/target/avr/cpu.c b/target/avr/cpu.c > new file mode 100644 > index 0000000000..dae56d7845 > --- /dev/null > +++ b/target/avr/cpu.c > @@ -0,0 +1,576 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu/qemu-print.h" > +#include "exec/exec-all.h" > +#include "cpu.h" > + > +static void avr_cpu_set_pc(CPUState *cs, vaddr value) > +{ > + AVRCPU *cpu =3D AVR_CPU(cs); > + > + cpu->env.pc_w =3D value / 2; /* internally PC points to words */ > +} > + > +static bool avr_cpu_has_work(CPUState *cs) > +{ > + AVRCPU *cpu =3D AVR_CPU(cs); > + CPUAVRState *env =3D &cpu->env; > + > + return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_= RESET)) > + && cpu_interrupts_enabled(env); > +} > + > +static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *= tb) > +{ > + AVRCPU *cpu =3D AVR_CPU(cs); > + CPUAVRState *env =3D &cpu->env; > + > + env->pc_w =3D tb->pc / 2; /* internally PC points to words */ > +} > + > +static void avr_cpu_reset(CPUState *cs) > +{ > + AVRCPU *cpu =3D AVR_CPU(cs); > + AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(cpu); > + CPUAVRState *env =3D &cpu->env; > + > + mcc->parent_reset(cs); > + > + env->pc_w =3D 0; > + env->sregI =3D 1; > + env->sregC =3D 0; > + env->sregZ =3D 0; > + env->sregN =3D 0; > + env->sregV =3D 0; > + env->sregS =3D 0; > + env->sregH =3D 0; > + env->sregT =3D 0; > + > + env->rampD =3D 0; > + env->rampX =3D 0; > + env->rampY =3D 0; > + env->rampZ =3D 0; > + env->eind =3D 0; > + env->sp =3D 0; > + > + env->skip =3D 0; > + > + memset(env->r, 0, sizeof(env->r)); > + > + tlb_flush(cs); > +} > + > +static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info= ) > +{ > + info->mach =3D bfd_arch_avr; > + info->print_insn =3D NULL; Why not implement the dump_ASM code? This is very useful... Richard what is your position on this? I'd rather enforce this as a=20 requirement for each ports. > +} > + [...]