From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FB55C432C2 for ; Thu, 26 Sep 2019 06:54:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 58F72222BE for ; Thu, 26 Sep 2019 06:54:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 58F72222BE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:59774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDNfy-0005SA-E7 for qemu-devel@archiver.kernel.org; Thu, 26 Sep 2019 02:54:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51383) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDNeK-00044W-FT for qemu-devel@nongnu.org; Thu, 26 Sep 2019 02:53:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDNeJ-0005RG-2p for qemu-devel@nongnu.org; Thu, 26 Sep 2019 02:53:12 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42062) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iDNeF-0005MI-2w; Thu, 26 Sep 2019 02:53:07 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4C1297FDF4; Thu, 26 Sep 2019 06:53:06 +0000 (UTC) Received: from [10.36.117.64] (ovpn-117-64.ams2.redhat.com [10.36.117.64]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2311C5D9CC; Thu, 26 Sep 2019 06:53:03 +0000 (UTC) Subject: Re: [PATCH v4 6/9] target/arm/kvm64: max cpu: Enable SVE when available To: Andrew Jones , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20190924113105.19076-1-drjones@redhat.com> <20190924113105.19076-7-drjones@redhat.com> From: Auger Eric Message-ID: <7524af40-3f53-40e2-03e3-e1896bd26858@redhat.com> Date: Thu, 26 Sep 2019 08:53:02 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190924113105.19076-7-drjones@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 26 Sep 2019 06:53:06 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, armbru@redhat.com, imammedo@redhat.com, alex.bennee@linaro.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Drew, On 9/24/19 1:31 PM, Andrew Jones wrote: > Enable SVE in the KVM guest when the 'max' cpu type is configured > and KVM supports it. KVM SVE requires use of the new finalize > vcpu ioctl, so we add that now too. For starters SVE can only be > turned on or off, getting all vector lengths the host CPU supports > when on. We'll add the other SVE CPU properties in later patches. > > Signed-off-by: Andrew Jones > Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Eric > --- > target/arm/cpu64.c | 17 ++++++++++++++--- > target/arm/kvm.c | 5 +++++ > target/arm/kvm64.c | 20 +++++++++++++++++++- > target/arm/kvm_arm.h | 27 +++++++++++++++++++++++++++ > tests/arm-cpu-features.c | 1 + > 5 files changed, 66 insertions(+), 4 deletions(-) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 606e3eceb9c0..b7eff4e1e107 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -481,6 +481,11 @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, > return; > } > > + if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) { > + error_setg(errp, "'sve' feature not supported by KVM on this host"); > + return; > + } > + > t = cpu->isar.id_aa64pfr0; > t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); > cpu->isar.id_aa64pfr0 = t; > @@ -495,11 +500,16 @@ static void aarch64_max_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > uint32_t vq; > + uint64_t t; > > if (kvm_enabled()) { > kvm_arm_set_cpu_features_from_host(cpu); > + if (kvm_arm_sve_supported(CPU(cpu))) { > + t = cpu->isar.id_aa64pfr0; > + t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); > + cpu->isar.id_aa64pfr0 = t; > + } > } else { > - uint64_t t; > uint32_t u; > aarch64_a57_initfn(obj); > > @@ -600,8 +610,6 @@ static void aarch64_max_initfn(Object *obj) > > object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, > cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); > - object_property_add(obj, "sve", "bool", cpu_arm_get_sve, > - cpu_arm_set_sve, NULL, NULL, &error_fatal); > > for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { > char name[8]; > @@ -610,6 +618,9 @@ static void aarch64_max_initfn(Object *obj) > cpu_arm_set_sve_vq, NULL, NULL, &error_fatal); > } > } > + > + object_property_add(obj, "sve", "bool", cpu_arm_get_sve, > + cpu_arm_set_sve, NULL, NULL, &error_fatal); > } > > struct ARMCPUInfo { > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index b2eaa50b8df9..72569f71236e 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -51,6 +51,11 @@ int kvm_arm_vcpu_init(CPUState *cs) > return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); > } > > +int kvm_arm_vcpu_finalize(CPUState *cs, int feature) > +{ > + return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); > +} > + > void kvm_arm_init_serror_injection(CPUState *cs) > { > cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state, > diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c > index ea454c613919..fc62bab8684e 100644 > --- a/target/arm/kvm64.c > +++ b/target/arm/kvm64.c > @@ -602,6 +602,13 @@ bool kvm_arm_aarch32_supported(CPUState *cpu) > return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT); > } > > +bool kvm_arm_sve_supported(CPUState *cpu) > +{ > + KVMState *s = KVM_STATE(current_machine->accelerator); > + > + return kvm_check_extension(s, KVM_CAP_ARM_SVE); > +} > + > #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 > > int kvm_arch_init_vcpu(CPUState *cs) > @@ -630,13 +637,17 @@ int kvm_arch_init_vcpu(CPUState *cs) > cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; > } > if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { > - cpu->has_pmu = false; > + cpu->has_pmu = false; > } > if (cpu->has_pmu) { > cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; > } else { > unset_feature(&env->features, ARM_FEATURE_PMU); > } > + if (cpu_isar_feature(aa64_sve, cpu)) { > + assert(kvm_arm_sve_supported(cs)); > + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; > + } > > /* Do KVM_ARM_VCPU_INIT ioctl */ > ret = kvm_arm_vcpu_init(cs); > @@ -644,6 +655,13 @@ int kvm_arch_init_vcpu(CPUState *cs) > return ret; > } > > + if (cpu_isar_feature(aa64_sve, cpu)) { > + ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); > + if (ret) { > + return ret; > + } > + } > + > /* > * When KVM is in use, PSCI is emulated in-kernel and not by qemu. > * Currently KVM has its own idea about MPIDR assignment, so we > diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h > index b3106c8600af..1151877f97ea 100644 > --- a/target/arm/kvm_arm.h > +++ b/target/arm/kvm_arm.h > @@ -27,6 +27,20 @@ > */ > int kvm_arm_vcpu_init(CPUState *cs); > > +/** > + * kvm_arm_vcpu_finalize > + * @cs: CPUState > + * @feature: int > + * > + * Finalizes the configuration of the specified VCPU feature by > + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring > + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of > + * KVM's API documentation. > + * > + * Returns: 0 if success else < 0 error code > + */ > +int kvm_arm_vcpu_finalize(CPUState *cs, int feature); > + > /** > * kvm_arm_register_device: > * @mr: memory region for this device > @@ -225,6 +239,14 @@ bool kvm_arm_aarch32_supported(CPUState *cs); > */ > bool kvm_arm_pmu_supported(CPUState *cs); > > +/** > + * bool kvm_arm_sve_supported: > + * @cs: CPUState > + * > + * Returns true if the KVM VCPU can enable SVE and false otherwise. > + */ > +bool kvm_arm_sve_supported(CPUState *cs); > + > /** > * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the > * IPA address space supported by KVM > @@ -275,6 +297,11 @@ static inline bool kvm_arm_pmu_supported(CPUState *cs) > return false; > } > > +static inline bool kvm_arm_sve_supported(CPUState *cs) > +{ > + return false; > +} > + > static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms) > { > return -ENOENT; > diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c > index 9a2dd402b769..d50f98cb6aea 100644 > --- a/tests/arm-cpu-features.c > +++ b/tests/arm-cpu-features.c > @@ -386,6 +386,7 @@ static void test_query_cpu_model_expansion_kvm(const void *data) > > if (g_str_equal(qtest_get_arch(), "aarch64")) { > assert_has_feature(qts, "host", "aarch64"); > + assert_has_feature(qts, "max", "sve"); > > assert_error(qts, "cortex-a15", > "We cannot guarantee the CPU type 'cortex-a15' works " >