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([2001:b07:6468:f312:8dc6:5dd5:2c0a:6a9a]) by smtp.gmail.com with ESMTPSA id l15sm3565597wrv.39.2019.12.03.05.04.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Dec 2019 05:04:07 -0800 (PST) Subject: Re: [PATCH] hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS To: Thomas Huth , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, David Gibson , =?UTF-8?Q?Herv=c3=a9_Poussineau?= References: <20191203072922.14981-1-thuth@redhat.com> <2b5d3c2d-6982-03f6-26cc-7400440b990f@redhat.com> <8ca69db3-7dfa-0c4d-bc50-61a80eb574c1@redhat.com> <6966e660-688a-977e-c882-9cb44ef97574@redhat.com> From: Paolo Bonzini Message-ID: <7528162c-ce2f-985e-7f58-9267389edd33@redhat.com> Date: Tue, 3 Dec 2019 14:04:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-MC-Unique: 2xIZRS-nMeKhxIMnw_ighA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 03/12/19 10:15, Thomas Huth wrote: >>>> Maybe we can rename this as read_boot_order_mm, and the previous >>>> read_boot_order_pc as read_boot_order_io. >>> >>> I don't think it makes much sense. This was completely specific to the >>> "prep" machine, even the "40p" machine seems to prefer fw_cfg nowadays. >>> So let's simply remove this old stuff. >>> >>>> diff --git a/tests/endianness-test.c b/tests/endianness-test.c >>>> index 58527952a5..2798802c63 100644 >>>> --- a/tests/endianness-test.c >>>> +++ b/tests/endianness-test.c >>>> @@ -35,7 +35,7 @@ static const TestCase test_cases[] =3D { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { "mips64", "malta", 0x10000000, = .bswap =3D true }, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { "mips64el", "fulong2e", 0x1fd00= 000 }, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { "ppc", "g3beige", 0xfe000000, .= bswap =3D true, .superio =3D >>>> "i82378" }, >>>> -=C2=A0=C2=A0=C2=A0 { "ppc", "prep", 0x80000000, .bswap =3D true }, >>>> +=C2=A0=C2=A0=C2=A0 { "ppc", "40p", 0x80000000, .bswap =3D true }, >> >> ... here you access the Super I/O behind the PCI bridge via MMIO? >=20 > The difference is that this is an *arbitrary* address in I/O space > there. No, it's the base address of the ISA space, to which the tests add the address of the pc-testdev device. It's not any different from the 0x80000000 in boot-order-test. That said, I think it's a sensible objection that boot order doesn't come from m48t59 on 40p (does it not?). The m48t59-test could also be adjusted to test the 40p... the right way to do it would be to have an ISA bridge driver in qgraph, but that's a topic for a separate series. Thanks, Paolo > It's not an address of a certain PCI device like the m48t59 > behind a PCI-bridge. As long as it's possible to write and read from > this address, the test is working. Both, the "prep" and the "40p" > machine have the "raven-pcihost" device at this address, so in this case > the switch from "40p" to "prep" was easily possible. >=20 > Thomas >=20 >=20