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[109.43.178.102]) by smtp.gmail.com with ESMTPSA id o22-20020a1c7516000000b003f18372d540sm12443983wmc.14.2023.04.24.09.39.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Apr 2023 09:39:17 -0700 (PDT) Message-ID: <755fb6e3-1f2c-00d0-139c-7275825fbe69@redhat.com> Date: Mon, 24 Apr 2023 18:39:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH] hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit() Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Beniamino Galvani , Strahinja Jankovic References: <20230424152833.1334136-1-peter.maydell@linaro.org> From: Thomas Huth In-Reply-To: <20230424152833.1334136-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.171, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.194, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 24/04/2023 17.28, Peter Maydell wrote: > The Allwinner PIC model uses set_bit() and clear_bit() to update the > values in its irq_pending[] array when an interrupt arrives. However > it is using these functions wrongly: they work on an array of type > 'long', and it is passing an array of type 'uint32_t'. Because the > code manually figures out the right array element, this works on > little-endian hosts and on 32-bit big-endian hosts, where bits 0..31 > in a 'long' are in the same place as they are in a 'uint32_t'. > However it breaks on 64-bit big-endian hosts. > > Remove the use of set_bit() and clear_bit() in favour of using > deposit32() on the array element. This fixes a bug where on > big-endian 64-bit hosts the guest kernel would hang early on in > bootup. > > Cc: qemu-stable@nongnu.org > Signed-off-by: Peter Maydell > --- > hw/intc/allwinner-a10-pic.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c > index 8cca1248073..4875e68ba6a 100644 > --- a/hw/intc/allwinner-a10-pic.c > +++ b/hw/intc/allwinner-a10-pic.c > @@ -49,12 +49,9 @@ static void aw_a10_pic_update(AwA10PICState *s) > static void aw_a10_pic_set_irq(void *opaque, int irq, int level) > { > AwA10PICState *s = opaque; > + uint32_t *pending_reg = &s->irq_pending[irq / 32]; > > - if (level) { > - set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); > - } else { > - clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); > - } > + *pending_reg = deposit32(*pending_reg, irq % 32, 1, level); > aw_a10_pic_update(s); > } > Reviewed-by: Thomas Huth