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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fa35c2sm10084081f8f.25.2025.11.21.04.47.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Nov 2025 04:47:09 -0800 (PST) Message-ID: <759ec110-365f-488b-802d-c7bb1efe30bc@redhat.com> Date: Fri, 21 Nov 2025 13:47:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v3 03/21] hw/arm/smmuv3: Introduce secure registers Content-Language: en-US To: Tao Tang , Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Philippe Brucker , Mostafa Saleh References: <20251012150701.4127034-1-tangtao1634@phytium.com.cn> <20251012150701.4127034-4-tangtao1634@phytium.com.cn> From: Eric Auger In-Reply-To: <20251012150701.4127034-4-tangtao1634@phytium.com.cn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Tao, On 10/12/25 5:06 PM, Tao Tang wrote: > The Arm SMMUv3 architecture defines a set of registers for managing > secure transactions and context. > > This patch introduces the definitions for these secure registers within > the SMMUv3 device model internal header. > > Signed-off-by: Tao Tang Reviewed-by: Eric Auger Eric > --- > hw/arm/smmuv3-internal.h | 69 +++++++++++++++++++++++++++++++++++++++- > 1 file changed, 68 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 8d631ecf27..e420c5dc72 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -38,7 +38,7 @@ typedef enum SMMUTranslationClass { > SMMU_CLASS_IN, > } SMMUTranslationClass; > > -/* MMIO Registers */ > +/* MMIO Registers. Shared by Non-secure/Realm/Root states. */ > > REG32(IDR0, 0x0) > FIELD(IDR0, S2P, 0 , 1) > @@ -121,6 +121,7 @@ REG32(CR0, 0x20) > FIELD(CR0, CMDQEN, 3, 1) > > #define SMMU_CR0_RESERVED 0xFFFFFA20 > +#define SMMU_S_CR0_RESERVED 0xFFFFFC12 > > REG32(CR0ACK, 0x24) > REG32(CR1, 0x28) > @@ -179,6 +180,72 @@ REG32(EVENTQ_IRQ_CFG2, 0xbc) > > #define A_IDREGS 0xfd0 > > +#define SMMU_SECURE_REG_START 0x8000 /* Start of secure-only registers */ > + > +REG32(S_IDR0, 0x8000) > +REG32(S_IDR1, 0x8004) > + FIELD(S_IDR1, S_SIDSIZE, 0 , 6) > + FIELD(S_IDR1, SEL2, 29, 1) > + FIELD(S_IDR1, SECURE_IMPL, 31, 1) > + > +REG32(S_IDR2, 0x8008) > +REG32(S_IDR3, 0x800c) > +REG32(S_IDR4, 0x8010) > + > +REG32(S_CR0, 0x8020) > + FIELD(S_CR0, SMMUEN, 0, 1) > + FIELD(S_CR0, EVENTQEN, 2, 1) > + FIELD(S_CR0, CMDQEN, 3, 1) > + > +REG32(S_CR0ACK, 0x8024) > +REG32(S_CR1, 0x8028) > +REG32(S_CR2, 0x802c) > + > +REG32(S_INIT, 0x803c) > + FIELD(S_INIT, INV_ALL, 0, 1) > + > +REG32(S_GBPA, 0x8044) > + FIELD(S_GBPA, ABORT, 20, 1) > + FIELD(S_GBPA, UPDATE, 31, 1) > + > +REG32(S_IRQ_CTRL, 0x8050) > + FIELD(S_IRQ_CTRL, GERROR_IRQEN, 0, 1) > + FIELD(S_IRQ_CTRL, EVENTQ_IRQEN, 2, 1) > + > +REG32(S_IRQ_CTRLACK, 0x8054) > + > +REG32(S_GERROR, 0x8060) > + FIELD(S_GERROR, CMDQ_ERR, 0, 1) > + > +#define SMMU_GERROR_IRQ_CFG0_RESERVED 0x00FFFFFFFFFFFFFC > +#define SMMU_GERROR_IRQ_CFG2_RESERVED 0x000000000000003F > + > +#define SMMU_STRTAB_BASE_RESERVED 0x40FFFFFFFFFFFFC0 > +#define SMMU_QUEUE_BASE_RESERVED 0x40FFFFFFFFFFFFFF > +#define SMMU_EVENTQ_IRQ_CFG0_RESERVED 0x00FFFFFFFFFFFFFC > + > +REG32(S_GERRORN, 0x8064) > +REG64(S_GERROR_IRQ_CFG0, 0x8068) > +REG32(S_GERROR_IRQ_CFG1, 0x8070) > +REG32(S_GERROR_IRQ_CFG2, 0x8074) > +REG64(S_STRTAB_BASE, 0x8080) > +REG32(S_STRTAB_BASE_CFG, 0x8088) > + FIELD(S_STRTAB_BASE_CFG, LOG2SIZE, 0, 6) > + FIELD(S_STRTAB_BASE_CFG, SPLIT, 6, 5) > + FIELD(S_STRTAB_BASE_CFG, FMT, 16, 2) > + > +REG64(S_CMDQ_BASE, 0x8090) > +REG32(S_CMDQ_PROD, 0x8098) > +REG32(S_CMDQ_CONS, 0x809c) > + FIELD(S_CMDQ_CONS, ERR, 24, 7) > + > +REG64(S_EVENTQ_BASE, 0x80a0) > +REG32(S_EVENTQ_PROD, 0x80a8) > +REG32(S_EVENTQ_CONS, 0x80ac) > +REG64(S_EVENTQ_IRQ_CFG0, 0x80b0) > +REG32(S_EVENTQ_IRQ_CFG1, 0x80b8) > +REG32(S_EVENTQ_IRQ_CFG2, 0x80bc) > + > static inline int smmu_enabled(SMMUv3State *s) > { > return FIELD_EX32(s->cr[0], CR0, SMMUEN);