From: Richard Henderson <richard.henderson@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/5] target/riscv: Add initial support for native debug
Date: Fri, 29 Oct 2021 12:41:32 -0700 [thread overview]
Message-ID: <75aca9b0-50fb-8b58-68ca-fab28a4b632e@linaro.org> (raw)
In-Reply-To: <20211029152535.2055096-2-bin.meng@windriver.com>
On 10/29/21 8:25 AM, Bin Meng wrote:
> @@ -231,6 +232,10 @@ struct CPURISCVState {
> pmp_table_t pmp_state;
> target_ulong mseccfg;
>
> + /* trigger module */
> + target_ulong trigger_cur;
> + trigger_type2_t trigger_type2[TRIGGER_TYPE2_NUM];
You need to add a subsection to machine.c to migrate this state.
r~
next prev parent reply other threads:[~2021-10-29 20:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 15:25 [PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2021-10-29 15:25 ` [PATCH 1/5] target/riscv: Add initial support for native debug Bin Meng
2021-10-29 19:41 ` Richard Henderson [this message]
2021-10-29 15:25 ` [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2021-10-29 19:36 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 3/5] target/riscv: Add a config option for native debug Bin Meng
2021-10-29 19:34 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 4/5] target/riscv: csr: Hook debug CSR read/write Bin Meng
2021-10-29 15:25 ` [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2021-10-29 19:33 ` Richard Henderson
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