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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id u188sm3004714pfu.33.2020.04.21.20.29.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Apr 2020 20:29:59 -0700 (PDT) Subject: Re: [PATCH] target/arm: Implement SVE2 scatter store insns To: Stephen Long , qemu-devel@nongnu.org References: <20200420204203.13279-1-steplong@quicinc.com> From: Richard Henderson Message-ID: <75ad766b-c687-1b57-03dc-521bed73281a@linaro.org> Date: Tue, 21 Apr 2020 20:29:57 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200420204203.13279-1-steplong@quicinc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::42f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, apazos@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/20/20 1:42 PM, Stephen Long wrote: > +static bool trans_ST1_zprz_sve2(DisasContext *s, arg_ST1_zprz_sve2 *a) > +{ > + gen_helper_gvec_mem_scatter *fn; > + bool be = s->be_data == MO_BE; > + bool mte = s->mte_active[0]; > + > + if (!dc_isar_feature(aa64_sve2, s) || a->esz < a->msz > + || (a->msz == 0 && a->scale)) { > + return false; > + } > + if (!sve_access_check(s)) { > + return true; > + } > + switch (a->esz) { > + case MO_32: > + fn = scatter_store_fn32[mte][be][a->xs][a->msz]; > + break; > + case MO_64: > + fn = scatter_store_fn64[mte][be][a->xs][a->msz]; > + break; > + default: > + g_assert_not_reached(); > + } > + do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, > + cpu_reg_sp(s, a->rn), a->msz, true, fn); > + return true; > +} I was thinking of something more along the lines of static bool STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) { if (!dc_isar_feature(aa64_sve2, s)) { return false; } return trans_ST1_zprz(s, a); } The fields should be identical, and so decodetree should pick the same type for 'a', underneath all of the typedefs. If decodetree cannot find a common argument set for the two insns, we might need to help it along, like we do with e.g. &rri_esz. I don't know without trying if that will be required. r~