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[176.172.56.29]) by smtp.gmail.com with ESMTPSA id t18-20020a056402021200b0052fdfd8870bsm548764edv.89.2023.09.14.00.41.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 00:41:32 -0700 (PDT) Message-ID: <75ea5477-ca1b-7016-273c-abd6c36f4be4@linaro.org> Date: Thu, 14 Sep 2023 09:41:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H Content-Language: en-US To: Zhao Liu , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Yongwei Ma References: <20230914072159.1177582-1-zhao1.liu@linux.intel.com> <20230914072159.1177582-22-zhao1.liu@linux.intel.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230914072159.1177582-22-zhao1.liu@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 14/9/23 09:21, Zhao Liu wrote: > From: Zhao Liu > > The property x-l2-cache-topo will be used to change the L2 cache > topology in CPUID.04H. > > Now it allows user to set the L2 cache is shared in core level or > cluster level. > > If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache > topology will be overrode by the new topology setting. > > Here we expose to user "cluster" instead of "module", to be consistent > with "cluster-id" naming. > > Since CPUID.04H is used by intel CPUs, this property is available on > intel CPUs as for now. > > When necessary, it can be extended to CPUID.8000001DH for AMD CPUs. > > (Tested the cache topology in CPUID[0x04] leaf with "x-l2-cache-topo=[ > core|cluster]", and tested the live migration between the QEMUs w/ & > w/o this patch series.) > > Signed-off-by: Zhao Liu > Tested-by: Yongwei Ma > --- > Changes since v3: > * Add description about test for live migration compatibility. (Babu) > > Changes since v1: > * Rename MODULE branch to CPU_TOPO_LEVEL_MODULE to match the previous > renaming changes. > --- > target/i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- > target/i386/cpu.h | 2 ++ > 2 files changed, 35 insertions(+), 1 deletion(-) > @@ -8079,6 +8110,7 @@ static Property x86_cpu_properties[] = { > false), > DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, > true), > + DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level), We use the 'x-' prefix for unstable features, is it the case here? > DEFINE_PROP_END_OF_LIST() > };