From: Richard Henderson <richard.henderson@linaro.org>
To: Aaron Lindsay <aaron@os.amperecomputing.com>,
"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@xilinx.com>,
Wei Huang <wei@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
Michael Spradling <mspradli@codeaurora.org>,
Digant Desai <digantd@codeaurora.org>
Subject: Re: [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
Date: Fri, 7 Dec 2018 12:00:37 -0600 [thread overview]
Message-ID: <75ec3369-0f1c-0ea7-1fc5-9e2263f6f86e@linaro.org> (raw)
In-Reply-To: <20181205153242.GE5549@quinoa.localdomain>
On 12/5/18 9:32 AM, Aaron Lindsay wrote:
> On Dec 05 08:43, Aaron Lindsay wrote:
>> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
>> ---
>> target/arm/cpu.h | 4 ++--
>> target/arm/helper.c | 18 ++++++++++++++++--
>> 2 files changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index 304e6e47b3..4216fe22db 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -837,8 +837,8 @@ struct ARMCPU {
>> uint32_t id_pfr0;
>> uint32_t id_pfr1;
>> uint32_t id_dfr0;
>> - uint32_t pmceid0;
>> - uint32_t pmceid1;
>> + uint64_t pmceid0;
>> + uint64_t pmceid1;
>> uint32_t id_afr0;
>> uint32_t id_mmfr0;
>> uint32_t id_mmfr1;
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index 71be6fb578..fb6939e99c 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -5256,6 +5256,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>> } else {
>> define_arm_cp_regs(cpu, not_v7_cp_reginfo);
>> }
>> + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4) {
>
> After further discussion on my last version, this should be
>
> if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
> FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
>
> to guard against defining these registers for implementation-defined
> PMUs.
When id fields define values like 0b1111, that is a hint that the field should
be interpreted as signed, and you should still use a >= comparison. (See
D12.1.4, Principles of the ID scheme for fields in ID registers.)
A patch adding
#define FIELD_EX32S(storage, reg, field) \
sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX64S(storage, reg, field) \
sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
to include/hw/registerfields.h would be welcome and appropriate, I think.
r~
next prev parent reply other threads:[~2018-12-07 18:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-05 13:43 [Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 01/14] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0 Aaron Lindsay
2018-12-06 15:56 ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-12-05 15:32 ` Aaron Lindsay
2018-12-06 15:59 ` Peter Maydell
2018-12-07 18:00 ` Richard Henderson [this message]
2018-12-09 21:58 ` Peter Maydell
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC Aaron Lindsay
2018-12-05 13:43 ` [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-12-06 16:03 ` Peter Maydell
2018-12-11 14:46 ` Aaron Lindsay
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=75ec3369-0f1c-0ea7-1fc5-9e2263f6f86e@linaro.org \
--to=richard.henderson@linaro.org \
--cc=aaron@os.amperecomputing.com \
--cc=alistair.francis@xilinx.com \
--cc=crosthwaite.peter@gmail.com \
--cc=digantd@codeaurora.org \
--cc=mspradli@codeaurora.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=wei@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).