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Wed, 07 Feb 2024 00:47:30 -0800 (PST) Message-ID: <76017b2e-f519-480e-8ad5-b45fda1670d3@linaro.org> Date: Wed, 7 Feb 2024 09:47:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/13] hw/misc/mps2-scc: Factor out which-board conditionals Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240206132931.38376-1-peter.maydell@linaro.org> <20240206132931.38376-7-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240206132931.38376-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/24 14:29, Peter Maydell wrote: > The MPS SCC device has a lot of different flavours for the various > different MPS FPGA images, which look mostly similar but have > differences in how particular registers are handled. Currently we > deal with this with a lot of open-coded checks on scc_partno(), but > as we add more board types this is getting a bit hard to read. > > Factor out the conditions into some functions which we can > give more descriptive names to. > > Signed-off-by: Peter Maydell > --- > hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++-------------- > 1 file changed, 31 insertions(+), 14 deletions(-) > > diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c > index 6c1b1cd3795..02a80bacd71 100644 > --- a/hw/misc/mps2-scc.c > +++ b/hw/misc/mps2-scc.c > @@ -59,6 +59,30 @@ static int scc_partno(MPS2SCC *s) > return extract32(s->id, 4, 8); > } > > +/* Is CFG_REG2 present? */ > +static bool have_cfg2(MPS2SCC *s) > +{ > + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; > +} > + > +/* Is CFG_REG3 present? */ > +static bool have_cfg3(MPS2SCC *s) > +{ > + return scc_partno(s) != 0x524 && scc_partno(s) != 0x547; > +} Looking at next patch and nitpicking, if we want to avoid a switch() case use, this style is easier to review IMHO: static bool have_cfg2(MPS2SCC *s) { return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; } Anyway, already R-b.