[Qemu-devel] ARM: small fixes

[Qemu-devel] ARM: small fixes

[Laurent Desnogues]

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Two trivial fixes.

arm-semi.c:
   - add missing return for SYS_SYSTEM
helper.c:
   - fix initialization of cp15 c0, c[12]


Laurent

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[-- Attachment #2: arm.patch --]
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diff -ru -x .svn svn-ref/arm-semi.c svn/arm-semi.c
--- svn-ref/arm-semi.c	2008-06-09 08:52:48.000000000 +0200
+++ svn/arm-semi.c	2008-06-09 08:58:31.000000000 +0200
@@ -362,6 +362,7 @@
                 return (uint32_t)-1;
             ret = set_swi_errno(ts, system(s));
             unlock_user(s, ARG(0), 0);
+            return ret;
         }
     case SYS_ERRNO:
 #ifdef CONFIG_USER_ONLY
diff -ru -x .svn svn-ref/target-arm/helper.c svn/target-arm/helper.c
--- svn-ref/target-arm/helper.c	2008-06-09 08:52:48.000000000 +0200
+++ svn/target-arm/helper.c	2008-06-09 08:58:30.000000000 +0200
@@ -64,7 +64,7 @@
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
         memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
-        memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
+        memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         break;
     case ARM_CPUID_ARM11MPCORE:
@@ -76,7 +76,7 @@
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
         memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
-        memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
+        memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         break;
     case ARM_CPUID_CORTEXA8:
@@ -92,7 +92,7 @@
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
         memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
-        memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
+        memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         break;
     case ARM_CPUID_CORTEXM3: